#ifndef F28P65X_GPIO_H
#define F28P65X_GPIO_H

#ifdef __cplusplus
extern "C" {
#endif

//---------------------------------------------------------------------------
// GPIO Individual Register Bit Definitions:

struct GPACTRL_BITS
{                        // bits description
    Uint32 QUALPRD0 : 8; // 7:0 Qualification sampling period for GPIO0 to GPIO7
    Uint32 QUALPRD1 : 8; // 15:8 Qualification sampling period for GPIO8 to GPIO15
    Uint32 QUALPRD2 : 8; // 23:16 Qualification sampling period for GPIO16 to GPIO23
    Uint32 QUALPRD3 : 8; // 31:24 Qualification sampling period for GPIO24 to GPIO31
};

union GPACTRL_REG
{
    Uint32 all;
    struct GPACTRL_BITS bit;
};

struct GPAQSEL1_BITS
{                      // bits description
    Uint32 GPIO0  : 2; // 1:0 Select input qualification type for GPIO0
    Uint32 GPIO1  : 2; // 3:2 Select input qualification type for GPIO1
    Uint32 GPIO2  : 2; // 5:4 Select input qualification type for GPIO2
    Uint32 GPIO3  : 2; // 7:6 Select input qualification type for GPIO3
    Uint32 GPIO4  : 2; // 9:8 Select input qualification type for GPIO4
    Uint32 GPIO5  : 2; // 11:10 Select input qualification type for GPIO5
    Uint32 GPIO6  : 2; // 13:12 Select input qualification type for GPIO6
    Uint32 GPIO7  : 2; // 15:14 Select input qualification type for GPIO7
    Uint32 GPIO8  : 2; // 17:16 Select input qualification type for GPIO8
    Uint32 GPIO9  : 2; // 19:18 Select input qualification type for GPIO9
    Uint32 GPIO10 : 2; // 21:20 Select input qualification type for GPIO10
    Uint32 GPIO11 : 2; // 23:22 Select input qualification type for GPIO11
    Uint32 GPIO12 : 2; // 25:24 Select input qualification type for GPIO12
    Uint32 GPIO13 : 2; // 27:26 Select input qualification type for GPIO13
    Uint32 GPIO14 : 2; // 29:28 Select input qualification type for GPIO14
    Uint32 GPIO15 : 2; // 31:30 Select input qualification type for GPIO15
};

union GPAQSEL1_REG
{
    Uint32 all;
    struct GPAQSEL1_BITS bit;
};

struct GPAQSEL2_BITS
{                      // bits description
    Uint32 GPIO16 : 2; // 1:0 Select input qualification type for GPIO16
    Uint32 GPIO17 : 2; // 3:2 Select input qualification type for GPIO17
    Uint32 GPIO18 : 2; // 5:4 Select input qualification type for GPIO18
    Uint32 GPIO19 : 2; // 7:6 Select input qualification type for GPIO19
    Uint32 GPIO20 : 2; // 9:8 Select input qualification type for GPIO20
    Uint32 GPIO21 : 2; // 11:10 Select input qualification type for GPIO21
    Uint32 GPIO22 : 2; // 13:12 Select input qualification type for GPIO22
    Uint32 GPIO23 : 2; // 15:14 Select input qualification type for GPIO23
    Uint32 GPIO24 : 2; // 17:16 Select input qualification type for GPIO24
    Uint32 GPIO25 : 2; // 19:18 Select input qualification type for GPIO25
    Uint32 GPIO26 : 2; // 21:20 Select input qualification type for GPIO26
    Uint32 GPIO27 : 2; // 23:22 Select input qualification type for GPIO27
    Uint32 GPIO28 : 2; // 25:24 Select input qualification type for GPIO28
    Uint32 GPIO29 : 2; // 27:26 Select input qualification type for GPIO29
    Uint32 GPIO30 : 2; // 29:28 Select input qualification type for GPIO30
    Uint32 GPIO31 : 2; // 31:30 Select input qualification type for GPIO31
};

union GPAQSEL2_REG
{
    Uint32 all;
    struct GPAQSEL2_BITS bit;
};

struct GPAMUX1_BITS
{                      // bits description
    Uint32 GPIO0  : 2; // 1:0 Defines pin-muxing selection for GPIO0
    Uint32 GPIO1  : 2; // 3:2 Defines pin-muxing selection for GPIO1
    Uint32 GPIO2  : 2; // 5:4 Defines pin-muxing selection for GPIO2
    Uint32 GPIO3  : 2; // 7:6 Defines pin-muxing selection for GPIO3
    Uint32 GPIO4  : 2; // 9:8 Defines pin-muxing selection for GPIO4
    Uint32 GPIO5  : 2; // 11:10 Defines pin-muxing selection for GPIO5
    Uint32 GPIO6  : 2; // 13:12 Defines pin-muxing selection for GPIO6
    Uint32 GPIO7  : 2; // 15:14 Defines pin-muxing selection for GPIO7
    Uint32 GPIO8  : 2; // 17:16 Defines pin-muxing selection for GPIO8
    Uint32 GPIO9  : 2; // 19:18 Defines pin-muxing selection for GPIO9
    Uint32 GPIO10 : 2; // 21:20 Defines pin-muxing selection for GPIO10
    Uint32 GPIO11 : 2; // 23:22 Defines pin-muxing selection for GPIO11
    Uint32 GPIO12 : 2; // 25:24 Defines pin-muxing selection for GPIO12
    Uint32 GPIO13 : 2; // 27:26 Defines pin-muxing selection for GPIO13
    Uint32 GPIO14 : 2; // 29:28 Defines pin-muxing selection for GPIO14
    Uint32 GPIO15 : 2; // 31:30 Defines pin-muxing selection for GPIO15
};

union GPAMUX1_REG
{
    Uint32 all;
    struct GPAMUX1_BITS bit;
};

struct GPAMUX2_BITS
{                      // bits description
    Uint32 GPIO16 : 2; // 1:0 Defines pin-muxing selection for GPIO16
    Uint32 GPIO17 : 2; // 3:2 Defines pin-muxing selection for GPIO17
    Uint32 GPIO18 : 2; // 5:4 Defines pin-muxing selection for GPIO18
    Uint32 GPIO19 : 2; // 7:6 Defines pin-muxing selection for GPIO19
    Uint32 GPIO20 : 2; // 9:8 Defines pin-muxing selection for GPIO20
    Uint32 GPIO21 : 2; // 11:10 Defines pin-muxing selection for GPIO21
    Uint32 GPIO22 : 2; // 13:12 Defines pin-muxing selection for GPIO22
    Uint32 GPIO23 : 2; // 15:14 Defines pin-muxing selection for GPIO23
    Uint32 GPIO24 : 2; // 17:16 Defines pin-muxing selection for GPIO24
    Uint32 GPIO25 : 2; // 19:18 Defines pin-muxing selection for GPIO25
    Uint32 GPIO26 : 2; // 21:20 Defines pin-muxing selection for GPIO26
    Uint32 GPIO27 : 2; // 23:22 Defines pin-muxing selection for GPIO27
    Uint32 GPIO28 : 2; // 25:24 Defines pin-muxing selection for GPIO28
    Uint32 GPIO29 : 2; // 27:26 Defines pin-muxing selection for GPIO29
    Uint32 GPIO30 : 2; // 29:28 Defines pin-muxing selection for GPIO30
    Uint32 GPIO31 : 2; // 31:30 Defines pin-muxing selection for GPIO31
};

union GPAMUX2_REG
{
    Uint32 all;
    struct GPAMUX2_BITS bit;
};

struct GPADIR_BITS
{                      // bits description
    Uint32 GPIO0  : 1; // 0 Defines direction for this pin in GPIO mode
    Uint32 GPIO1  : 1; // 1 Defines direction for this pin in GPIO mode
    Uint32 GPIO2  : 1; // 2 Defines direction for this pin in GPIO mode
    Uint32 GPIO3  : 1; // 3 Defines direction for this pin in GPIO mode
    Uint32 GPIO4  : 1; // 4 Defines direction for this pin in GPIO mode
    Uint32 GPIO5  : 1; // 5 Defines direction for this pin in GPIO mode
    Uint32 GPIO6  : 1; // 6 Defines direction for this pin in GPIO mode
    Uint32 GPIO7  : 1; // 7 Defines direction for this pin in GPIO mode
    Uint32 GPIO8  : 1; // 8 Defines direction for this pin in GPIO mode
    Uint32 GPIO9  : 1; // 9 Defines direction for this pin in GPIO mode
    Uint32 GPIO10 : 1; // 10 Defines direction for this pin in GPIO mode
    Uint32 GPIO11 : 1; // 11 Defines direction for this pin in GPIO mode
    Uint32 GPIO12 : 1; // 12 Defines direction for this pin in GPIO mode
    Uint32 GPIO13 : 1; // 13 Defines direction for this pin in GPIO mode
    Uint32 GPIO14 : 1; // 14 Defines direction for this pin in GPIO mode
    Uint32 GPIO15 : 1; // 15 Defines direction for this pin in GPIO mode
    Uint32 GPIO16 : 1; // 16 Defines direction for this pin in GPIO mode
    Uint32 GPIO17 : 1; // 17 Defines direction for this pin in GPIO mode
    Uint32 GPIO18 : 1; // 18 Defines direction for this pin in GPIO mode
    Uint32 GPIO19 : 1; // 19 Defines direction for this pin in GPIO mode
    Uint32 GPIO20 : 1; // 20 Defines direction for this pin in GPIO mode
    Uint32 GPIO21 : 1; // 21 Defines direction for this pin in GPIO mode
    Uint32 GPIO22 : 1; // 22 Defines direction for this pin in GPIO mode
    Uint32 GPIO23 : 1; // 23 Defines direction for this pin in GPIO mode
    Uint32 GPIO24 : 1; // 24 Defines direction for this pin in GPIO mode
    Uint32 GPIO25 : 1; // 25 Defines direction for this pin in GPIO mode
    Uint32 GPIO26 : 1; // 26 Defines direction for this pin in GPIO mode
    Uint32 GPIO27 : 1; // 27 Defines direction for this pin in GPIO mode
    Uint32 GPIO28 : 1; // 28 Defines direction for this pin in GPIO mode
    Uint32 GPIO29 : 1; // 29 Defines direction for this pin in GPIO mode
    Uint32 GPIO30 : 1; // 30 Defines direction for this pin in GPIO mode
    Uint32 GPIO31 : 1; // 31 Defines direction for this pin in GPIO mode
};

union GPADIR_REG
{
    Uint32 all;
    struct GPADIR_BITS bit;
};

struct GPAPUD_BITS
{                      // bits description
    Uint32 GPIO0  : 1; // 0 Pull-Up Disable control for this pin
    Uint32 GPIO1  : 1; // 1 Pull-Up Disable control for this pin
    Uint32 GPIO2  : 1; // 2 Pull-Up Disable control for this pin
    Uint32 GPIO3  : 1; // 3 Pull-Up Disable control for this pin
    Uint32 GPIO4  : 1; // 4 Pull-Up Disable control for this pin
    Uint32 GPIO5  : 1; // 5 Pull-Up Disable control for this pin
    Uint32 GPIO6  : 1; // 6 Pull-Up Disable control for this pin
    Uint32 GPIO7  : 1; // 7 Pull-Up Disable control for this pin
    Uint32 GPIO8  : 1; // 8 Pull-Up Disable control for this pin
    Uint32 GPIO9  : 1; // 9 Pull-Up Disable control for this pin
    Uint32 GPIO10 : 1; // 10 Pull-Up Disable control for this pin
    Uint32 GPIO11 : 1; // 11 Pull-Up Disable control for this pin
    Uint32 GPIO12 : 1; // 12 Pull-Up Disable control for this pin
    Uint32 GPIO13 : 1; // 13 Pull-Up Disable control for this pin
    Uint32 GPIO14 : 1; // 14 Pull-Up Disable control for this pin
    Uint32 GPIO15 : 1; // 15 Pull-Up Disable control for this pin
    Uint32 GPIO16 : 1; // 16 Pull-Up Disable control for this pin
    Uint32 GPIO17 : 1; // 17 Pull-Up Disable control for this pin
    Uint32 GPIO18 : 1; // 18 Pull-Up Disable control for this pin
    Uint32 GPIO19 : 1; // 19 Pull-Up Disable control for this pin
    Uint32 GPIO20 : 1; // 20 Pull-Up Disable control for this pin
    Uint32 GPIO21 : 1; // 21 Pull-Up Disable control for this pin
    Uint32 GPIO22 : 1; // 22 Pull-Up Disable control for this pin
    Uint32 GPIO23 : 1; // 23 Pull-Up Disable control for this pin
    Uint32 GPIO24 : 1; // 24 Pull-Up Disable control for this pin
    Uint32 GPIO25 : 1; // 25 Pull-Up Disable control for this pin
    Uint32 GPIO26 : 1; // 26 Pull-Up Disable control for this pin
    Uint32 GPIO27 : 1; // 27 Pull-Up Disable control for this pin
    Uint32 GPIO28 : 1; // 28 Pull-Up Disable control for this pin
    Uint32 GPIO29 : 1; // 29 Pull-Up Disable control for this pin
    Uint32 GPIO30 : 1; // 30 Pull-Up Disable control for this pin
    Uint32 GPIO31 : 1; // 31 Pull-Up Disable control for this pin
};

union GPAPUD_REG
{
    Uint32 all;
    struct GPAPUD_BITS bit;
};

struct GPAINV_BITS
{                      // bits description
    Uint32 GPIO0  : 1; // 0 Input inversion control for this pin
    Uint32 GPIO1  : 1; // 1 Input inversion control for this pin
    Uint32 GPIO2  : 1; // 2 Input inversion control for this pin
    Uint32 GPIO3  : 1; // 3 Input inversion control for this pin
    Uint32 GPIO4  : 1; // 4 Input inversion control for this pin
    Uint32 GPIO5  : 1; // 5 Input inversion control for this pin
    Uint32 GPIO6  : 1; // 6 Input inversion control for this pin
    Uint32 GPIO7  : 1; // 7 Input inversion control for this pin
    Uint32 GPIO8  : 1; // 8 Input inversion control for this pin
    Uint32 GPIO9  : 1; // 9 Input inversion control for this pin
    Uint32 GPIO10 : 1; // 10 Input inversion control for this pin
    Uint32 GPIO11 : 1; // 11 Input inversion control for this pin
    Uint32 GPIO12 : 1; // 12 Input inversion control for this pin
    Uint32 GPIO13 : 1; // 13 Input inversion control for this pin
    Uint32 GPIO14 : 1; // 14 Input inversion control for this pin
    Uint32 GPIO15 : 1; // 15 Input inversion control for this pin
    Uint32 GPIO16 : 1; // 16 Input inversion control for this pin
    Uint32 GPIO17 : 1; // 17 Input inversion control for this pin
    Uint32 GPIO18 : 1; // 18 Input inversion control for this pin
    Uint32 GPIO19 : 1; // 19 Input inversion control for this pin
    Uint32 GPIO20 : 1; // 20 Input inversion control for this pin
    Uint32 GPIO21 : 1; // 21 Input inversion control for this pin
    Uint32 GPIO22 : 1; // 22 Input inversion control for this pin
    Uint32 GPIO23 : 1; // 23 Input inversion control for this pin
    Uint32 GPIO24 : 1; // 24 Input inversion control for this pin
    Uint32 GPIO25 : 1; // 25 Input inversion control for this pin
    Uint32 GPIO26 : 1; // 26 Input inversion control for this pin
    Uint32 GPIO27 : 1; // 27 Input inversion control for this pin
    Uint32 GPIO28 : 1; // 28 Input inversion control for this pin
    Uint32 GPIO29 : 1; // 29 Input inversion control for this pin
    Uint32 GPIO30 : 1; // 30 Input inversion control for this pin
    Uint32 GPIO31 : 1; // 31 Input inversion control for this pin
};

union GPAINV_REG
{
    Uint32 all;
    struct GPAINV_BITS bit;
};

struct GPAODR_BITS
{                      // bits description
    Uint32 GPIO0  : 1; // 0 Output Open-Drain control for this pin
    Uint32 GPIO1  : 1; // 1 Output Open-Drain control for this pin
    Uint32 GPIO2  : 1; // 2 Output Open-Drain control for this pin
    Uint32 GPIO3  : 1; // 3 Output Open-Drain control for this pin
    Uint32 GPIO4  : 1; // 4 Output Open-Drain control for this pin
    Uint32 GPIO5  : 1; // 5 Output Open-Drain control for this pin
    Uint32 GPIO6  : 1; // 6 Output Open-Drain control for this pin
    Uint32 GPIO7  : 1; // 7 Output Open-Drain control for this pin
    Uint32 GPIO8  : 1; // 8 Output Open-Drain control for this pin
    Uint32 GPIO9  : 1; // 9 Output Open-Drain control for this pin
    Uint32 GPIO10 : 1; // 10 Output Open-Drain control for this pin
    Uint32 GPIO11 : 1; // 11 Output Open-Drain control for this pin
    Uint32 GPIO12 : 1; // 12 Output Open-Drain control for this pin
    Uint32 GPIO13 : 1; // 13 Output Open-Drain control for this pin
    Uint32 GPIO14 : 1; // 14 Output Open-Drain control for this pin
    Uint32 GPIO15 : 1; // 15 Output Open-Drain control for this pin
    Uint32 GPIO16 : 1; // 16 Output Open-Drain control for this pin
    Uint32 GPIO17 : 1; // 17 Output Open-Drain control for this pin
    Uint32 GPIO18 : 1; // 18 Output Open-Drain control for this pin
    Uint32 GPIO19 : 1; // 19 Output Open-Drain control for this pin
    Uint32 GPIO20 : 1; // 20 Output Open-Drain control for this pin
    Uint32 GPIO21 : 1; // 21 Output Open-Drain control for this pin
    Uint32 GPIO22 : 1; // 22 Output Open-Drain control for this pin
    Uint32 GPIO23 : 1; // 23 Output Open-Drain control for this pin
    Uint32 GPIO24 : 1; // 24 Output Open-Drain control for this pin
    Uint32 GPIO25 : 1; // 25 Output Open-Drain control for this pin
    Uint32 GPIO26 : 1; // 26 Output Open-Drain control for this pin
    Uint32 GPIO27 : 1; // 27 Output Open-Drain control for this pin
    Uint32 GPIO28 : 1; // 28 Output Open-Drain control for this pin
    Uint32 GPIO29 : 1; // 29 Output Open-Drain control for this pin
    Uint32 GPIO30 : 1; // 30 Output Open-Drain control for this pin
    Uint32 GPIO31 : 1; // 31 Output Open-Drain control for this pin
};

union GPAODR_REG
{
    Uint32 all;
    struct GPAODR_BITS bit;
};

struct GPAGMUX1_BITS
{                      // bits description
    Uint32 GPIO0  : 2; // 1:0 Defines pin-muxing selection for GPIO0
    Uint32 GPIO1  : 2; // 3:2 Defines pin-muxing selection for GPIO1
    Uint32 GPIO2  : 2; // 5:4 Defines pin-muxing selection for GPIO2
    Uint32 GPIO3  : 2; // 7:6 Defines pin-muxing selection for GPIO3
    Uint32 GPIO4  : 2; // 9:8 Defines pin-muxing selection for GPIO4
    Uint32 GPIO5  : 2; // 11:10 Defines pin-muxing selection for GPIO5
    Uint32 GPIO6  : 2; // 13:12 Defines pin-muxing selection for GPIO6
    Uint32 GPIO7  : 2; // 15:14 Defines pin-muxing selection for GPIO7
    Uint32 GPIO8  : 2; // 17:16 Defines pin-muxing selection for GPIO8
    Uint32 GPIO9  : 2; // 19:18 Defines pin-muxing selection for GPIO9
    Uint32 GPIO10 : 2; // 21:20 Defines pin-muxing selection for GPIO10
    Uint32 GPIO11 : 2; // 23:22 Defines pin-muxing selection for GPIO11
    Uint32 GPIO12 : 2; // 25:24 Defines pin-muxing selection for GPIO12
    Uint32 GPIO13 : 2; // 27:26 Defines pin-muxing selection for GPIO13
    Uint32 GPIO14 : 2; // 29:28 Defines pin-muxing selection for GPIO14
    Uint32 GPIO15 : 2; // 31:30 Defines pin-muxing selection for GPIO15
};

union GPAGMUX1_REG
{
    Uint32 all;
    struct GPAGMUX1_BITS bit;
};

struct GPAGMUX2_BITS
{                      // bits description
    Uint32 GPIO16 : 2; // 1:0 Defines pin-muxing selection for GPIO16
    Uint32 GPIO17 : 2; // 3:2 Defines pin-muxing selection for GPIO17
    Uint32 GPIO18 : 2; // 5:4 Defines pin-muxing selection for GPIO18
    Uint32 GPIO19 : 2; // 7:6 Defines pin-muxing selection for GPIO19
    Uint32 GPIO20 : 2; // 9:8 Defines pin-muxing selection for GPIO20
    Uint32 GPIO21 : 2; // 11:10 Defines pin-muxing selection for GPIO21
    Uint32 GPIO22 : 2; // 13:12 Defines pin-muxing selection for GPIO22
    Uint32 GPIO23 : 2; // 15:14 Defines pin-muxing selection for GPIO23
    Uint32 GPIO24 : 2; // 17:16 Defines pin-muxing selection for GPIO24
    Uint32 GPIO25 : 2; // 19:18 Defines pin-muxing selection for GPIO25
    Uint32 GPIO26 : 2; // 21:20 Defines pin-muxing selection for GPIO26
    Uint32 GPIO27 : 2; // 23:22 Defines pin-muxing selection for GPIO27
    Uint32 GPIO28 : 2; // 25:24 Defines pin-muxing selection for GPIO28
    Uint32 GPIO29 : 2; // 27:26 Defines pin-muxing selection for GPIO29
    Uint32 GPIO30 : 2; // 29:28 Defines pin-muxing selection for GPIO30
    Uint32 GPIO31 : 2; // 31:30 Defines pin-muxing selection for GPIO31
};

union GPAGMUX2_REG
{
    Uint32 all;
    struct GPAGMUX2_BITS bit;
};

struct GPACSEL1_BITS
{                     // bits description
    Uint32 GPIO0 : 4; // 3:0 GPIO0 Controller CPU Select
    Uint32 GPIO1 : 4; // 7:4 GPIO1 Controller CPU Select
    Uint32 GPIO2 : 4; // 11:8 GPIO2 Controller CPU Select
    Uint32 GPIO3 : 4; // 15:12 GPIO3 Controller CPU Select
    Uint32 GPIO4 : 4; // 19:16 GPIO4 Controller CPU Select
    Uint32 GPIO5 : 4; // 23:20 GPIO5 Controller CPU Select
    Uint32 GPIO6 : 4; // 27:24 GPIO6 Controller CPU Select
    Uint32 GPIO7 : 4; // 31:28 GPIO7 Controller CPU Select
};

union GPACSEL1_REG
{
    Uint32 all;
    struct GPACSEL1_BITS bit;
};

struct GPACSEL2_BITS
{                      // bits description
    Uint32 GPIO8  : 4; // 3:0 GPIO8 Controller CPU Select
    Uint32 GPIO9  : 4; // 7:4 GPIO9 Controller CPU Select
    Uint32 GPIO10 : 4; // 11:8 GPIO10 Controller CPU Select
    Uint32 GPIO11 : 4; // 15:12 GPIO11 Controller CPU Select
    Uint32 GPIO12 : 4; // 19:16 GPIO12 Controller CPU Select
    Uint32 GPIO13 : 4; // 23:20 GPIO13 Controller CPU Select
    Uint32 GPIO14 : 4; // 27:24 GPIO14 Controller CPU Select
    Uint32 GPIO15 : 4; // 31:28 GPIO15 Controller CPU Select
};

union GPACSEL2_REG
{
    Uint32 all;
    struct GPACSEL2_BITS bit;
};

struct GPACSEL3_BITS
{                      // bits description
    Uint32 GPIO16 : 4; // 3:0 GPIO16 Controller CPU Select
    Uint32 GPIO17 : 4; // 7:4 GPIO17 Controller CPU Select
    Uint32 GPIO18 : 4; // 11:8 GPIO18 Controller CPU Select
    Uint32 GPIO19 : 4; // 15:12 GPIO19 Controller CPU Select
    Uint32 GPIO20 : 4; // 19:16 GPIO20 Controller CPU Select
    Uint32 GPIO21 : 4; // 23:20 GPIO21 Controller CPU Select
    Uint32 GPIO22 : 4; // 27:24 GPIO22 Controller CPU Select
    Uint32 GPIO23 : 4; // 31:28 GPIO23 Controller CPU Select
};

union GPACSEL3_REG
{
    Uint32 all;
    struct GPACSEL3_BITS bit;
};

struct GPACSEL4_BITS
{                      // bits description
    Uint32 GPIO24 : 4; // 3:0 GPIO24 Controller CPU Select
    Uint32 GPIO25 : 4; // 7:4 GPIO25 Controller CPU Select
    Uint32 GPIO26 : 4; // 11:8 GPIO26 Controller CPU Select
    Uint32 GPIO27 : 4; // 15:12 GPIO27 Controller CPU Select
    Uint32 GPIO28 : 4; // 19:16 GPIO28 Controller CPU Select
    Uint32 GPIO29 : 4; // 23:20 GPIO29 Controller CPU Select
    Uint32 GPIO30 : 4; // 27:24 GPIO30 Controller CPU Select
    Uint32 GPIO31 : 4; // 31:28 GPIO31 Controller CPU Select
};

union GPACSEL4_REG
{
    Uint32 all;
    struct GPACSEL4_BITS bit;
};

struct GPALOCK_BITS
{                      // bits description
    Uint32 GPIO0  : 1; // 0 Configuration Lock bit for this pin
    Uint32 GPIO1  : 1; // 1 Configuration Lock bit for this pin
    Uint32 GPIO2  : 1; // 2 Configuration Lock bit for this pin
    Uint32 GPIO3  : 1; // 3 Configuration Lock bit for this pin
    Uint32 GPIO4  : 1; // 4 Configuration Lock bit for this pin
    Uint32 GPIO5  : 1; // 5 Configuration Lock bit for this pin
    Uint32 GPIO6  : 1; // 6 Configuration Lock bit for this pin
    Uint32 GPIO7  : 1; // 7 Configuration Lock bit for this pin
    Uint32 GPIO8  : 1; // 8 Configuration Lock bit for this pin
    Uint32 GPIO9  : 1; // 9 Configuration Lock bit for this pin
    Uint32 GPIO10 : 1; // 10 Configuration Lock bit for this pin
    Uint32 GPIO11 : 1; // 11 Configuration Lock bit for this pin
    Uint32 GPIO12 : 1; // 12 Configuration Lock bit for this pin
    Uint32 GPIO13 : 1; // 13 Configuration Lock bit for this pin
    Uint32 GPIO14 : 1; // 14 Configuration Lock bit for this pin
    Uint32 GPIO15 : 1; // 15 Configuration Lock bit for this pin
    Uint32 GPIO16 : 1; // 16 Configuration Lock bit for this pin
    Uint32 GPIO17 : 1; // 17 Configuration Lock bit for this pin
    Uint32 GPIO18 : 1; // 18 Configuration Lock bit for this pin
    Uint32 GPIO19 : 1; // 19 Configuration Lock bit for this pin
    Uint32 GPIO20 : 1; // 20 Configuration Lock bit for this pin
    Uint32 GPIO21 : 1; // 21 Configuration Lock bit for this pin
    Uint32 GPIO22 : 1; // 22 Configuration Lock bit for this pin
    Uint32 GPIO23 : 1; // 23 Configuration Lock bit for this pin
    Uint32 GPIO24 : 1; // 24 Configuration Lock bit for this pin
    Uint32 GPIO25 : 1; // 25 Configuration Lock bit for this pin
    Uint32 GPIO26 : 1; // 26 Configuration Lock bit for this pin
    Uint32 GPIO27 : 1; // 27 Configuration Lock bit for this pin
    Uint32 GPIO28 : 1; // 28 Configuration Lock bit for this pin
    Uint32 GPIO29 : 1; // 29 Configuration Lock bit for this pin
    Uint32 GPIO30 : 1; // 30 Configuration Lock bit for this pin
    Uint32 GPIO31 : 1; // 31 Configuration Lock bit for this pin
};

union GPALOCK_REG
{
    Uint32 all;
    struct GPALOCK_BITS bit;
};

struct GPACR_BITS
{                      // bits description
    Uint32 GPIO0  : 1; // 0 Configuration lock commit bit for this pin
    Uint32 GPIO1  : 1; // 1 Configuration lock commit bit for this pin
    Uint32 GPIO2  : 1; // 2 Configuration lock commit bit for this pin
    Uint32 GPIO3  : 1; // 3 Configuration lock commit bit for this pin
    Uint32 GPIO4  : 1; // 4 Configuration lock commit bit for this pin
    Uint32 GPIO5  : 1; // 5 Configuration lock commit bit for this pin
    Uint32 GPIO6  : 1; // 6 Configuration lock commit bit for this pin
    Uint32 GPIO7  : 1; // 7 Configuration lock commit bit for this pin
    Uint32 GPIO8  : 1; // 8 Configuration lock commit bit for this pin
    Uint32 GPIO9  : 1; // 9 Configuration lock commit bit for this pin
    Uint32 GPIO10 : 1; // 10 Configuration lock commit bit for this pin
    Uint32 GPIO11 : 1; // 11 Configuration lock commit bit for this pin
    Uint32 GPIO12 : 1; // 12 Configuration lock commit bit for this pin
    Uint32 GPIO13 : 1; // 13 Configuration lock commit bit for this pin
    Uint32 GPIO14 : 1; // 14 Configuration lock commit bit for this pin
    Uint32 GPIO15 : 1; // 15 Configuration lock commit bit for this pin
    Uint32 GPIO16 : 1; // 16 Configuration lock commit bit for this pin
    Uint32 GPIO17 : 1; // 17 Configuration lock commit bit for this pin
    Uint32 GPIO18 : 1; // 18 Configuration lock commit bit for this pin
    Uint32 GPIO19 : 1; // 19 Configuration lock commit bit for this pin
    Uint32 GPIO20 : 1; // 20 Configuration lock commit bit for this pin
    Uint32 GPIO21 : 1; // 21 Configuration lock commit bit for this pin
    Uint32 GPIO22 : 1; // 22 Configuration lock commit bit for this pin
    Uint32 GPIO23 : 1; // 23 Configuration lock commit bit for this pin
    Uint32 GPIO24 : 1; // 24 Configuration lock commit bit for this pin
    Uint32 GPIO25 : 1; // 25 Configuration lock commit bit for this pin
    Uint32 GPIO26 : 1; // 26 Configuration lock commit bit for this pin
    Uint32 GPIO27 : 1; // 27 Configuration lock commit bit for this pin
    Uint32 GPIO28 : 1; // 28 Configuration lock commit bit for this pin
    Uint32 GPIO29 : 1; // 29 Configuration lock commit bit for this pin
    Uint32 GPIO30 : 1; // 30 Configuration lock commit bit for this pin
    Uint32 GPIO31 : 1; // 31 Configuration lock commit bit for this pin
};

union GPACR_REG
{
    Uint32 all;
    struct GPACR_BITS bit;
};

struct GPBCTRL_BITS
{                        // bits description
    Uint32 QUALPRD0 : 8; // 7:0 Qualification sampling period for GPIO32 to GPIO39
    Uint32 QUALPRD1 : 8; // 15:8 Qualification sampling period for GPIO40 to GPIO47
    Uint32 QUALPRD2 : 8; // 23:16 Qualification sampling period for GPIO48 to GPIO55
    Uint32 QUALPRD3 : 8; // 31:24 Qualification sampling period for GPIO56 to GPIO63
};

union GPBCTRL_REG
{
    Uint32 all;
    struct GPBCTRL_BITS bit;
};

struct GPBQSEL1_BITS
{                      // bits description
    Uint32 GPIO32 : 2; // 1:0 Select input qualification type for GPIO32
    Uint32 GPIO33 : 2; // 3:2 Select input qualification type for GPIO33
    Uint32 GPIO34 : 2; // 5:4 Select input qualification type for GPIO34
    Uint32 GPIO35 : 2; // 7:6 Select input qualification type for GPIO35
    Uint32 GPIO36 : 2; // 9:8 Select input qualification type for GPIO36
    Uint32 GPIO37 : 2; // 11:10 Select input qualification type for GPIO37
    Uint32 GPIO38 : 2; // 13:12 Select input qualification type for GPIO38
    Uint32 GPIO39 : 2; // 15:14 Select input qualification type for GPIO39
    Uint32 GPIO40 : 2; // 17:16 Select input qualification type for GPIO40
    Uint32 GPIO41 : 2; // 19:18 Select input qualification type for GPIO41
    Uint32 GPIO42 : 2; // 21:20 Select input qualification type for GPIO42
    Uint32 GPIO43 : 2; // 23:22 Select input qualification type for GPIO43
    Uint32 GPIO44 : 2; // 25:24 Select input qualification type for GPIO44
    Uint32 GPIO45 : 2; // 27:26 Select input qualification type for GPIO45
    Uint32 GPIO46 : 2; // 29:28 Select input qualification type for GPIO46
    Uint32 GPIO47 : 2; // 31:30 Select input qualification type for GPIO47
};

union GPBQSEL1_REG
{
    Uint32 all;
    struct GPBQSEL1_BITS bit;
};

struct GPBQSEL2_BITS
{                      // bits description
    Uint32 GPIO48 : 2; // 1:0 Select input qualification type for GPIO48
    Uint32 GPIO49 : 2; // 3:2 Select input qualification type for GPIO49
    Uint32 GPIO50 : 2; // 5:4 Select input qualification type for GPIO50
    Uint32 GPIO51 : 2; // 7:6 Select input qualification type for GPIO51
    Uint32 GPIO52 : 2; // 9:8 Select input qualification type for GPIO52
    Uint32 GPIO53 : 2; // 11:10 Select input qualification type for GPIO53
    Uint32 GPIO54 : 2; // 13:12 Select input qualification type for GPIO54
    Uint32 GPIO55 : 2; // 15:14 Select input qualification type for GPIO55
    Uint32 GPIO56 : 2; // 17:16 Select input qualification type for GPIO56
    Uint32 GPIO57 : 2; // 19:18 Select input qualification type for GPIO57
    Uint32 GPIO58 : 2; // 21:20 Select input qualification type for GPIO58
    Uint32 GPIO59 : 2; // 23:22 Select input qualification type for GPIO59
    Uint32 GPIO60 : 2; // 25:24 Select input qualification type for GPIO60
    Uint32 GPIO61 : 2; // 27:26 Select input qualification type for GPIO61
    Uint32 GPIO62 : 2; // 29:28 Select input qualification type for GPIO62
    Uint32 GPIO63 : 2; // 31:30 Select input qualification type for GPIO63
};

union GPBQSEL2_REG
{
    Uint32 all;
    struct GPBQSEL2_BITS bit;
};

struct GPBMUX1_BITS
{                      // bits description
    Uint32 GPIO32 : 2; // 1:0 Defines pin-muxing selection for GPIO32
    Uint32 GPIO33 : 2; // 3:2 Defines pin-muxing selection for GPIO33
    Uint32 GPIO34 : 2; // 5:4 Defines pin-muxing selection for GPIO34
    Uint32 GPIO35 : 2; // 7:6 Defines pin-muxing selection for GPIO35
    Uint32 GPIO36 : 2; // 9:8 Defines pin-muxing selection for GPIO36
    Uint32 GPIO37 : 2; // 11:10 Defines pin-muxing selection for GPIO37
    Uint32 GPIO38 : 2; // 13:12 Defines pin-muxing selection for GPIO38
    Uint32 GPIO39 : 2; // 15:14 Defines pin-muxing selection for GPIO39
    Uint32 GPIO40 : 2; // 17:16 Defines pin-muxing selection for GPIO40
    Uint32 GPIO41 : 2; // 19:18 Defines pin-muxing selection for GPIO41
    Uint32 GPIO42 : 2; // 21:20 Defines pin-muxing selection for GPIO42
    Uint32 GPIO43 : 2; // 23:22 Defines pin-muxing selection for GPIO43
    Uint32 GPIO44 : 2; // 25:24 Defines pin-muxing selection for GPIO44
    Uint32 GPIO45 : 2; // 27:26 Defines pin-muxing selection for GPIO45
    Uint32 GPIO46 : 2; // 29:28 Defines pin-muxing selection for GPIO46
    Uint32 GPIO47 : 2; // 31:30 Defines pin-muxing selection for GPIO47
};

union GPBMUX1_REG
{
    Uint32 all;
    struct GPBMUX1_BITS bit;
};

struct GPBMUX2_BITS
{                      // bits description
    Uint32 GPIO48 : 2; // 1:0 Defines pin-muxing selection for GPIO48
    Uint32 GPIO49 : 2; // 3:2 Defines pin-muxing selection for GPIO49
    Uint32 GPIO50 : 2; // 5:4 Defines pin-muxing selection for GPIO50
    Uint32 GPIO51 : 2; // 7:6 Defines pin-muxing selection for GPIO51
    Uint32 GPIO52 : 2; // 9:8 Defines pin-muxing selection for GPIO52
    Uint32 GPIO53 : 2; // 11:10 Defines pin-muxing selection for GPIO53
    Uint32 GPIO54 : 2; // 13:12 Defines pin-muxing selection for GPIO54
    Uint32 GPIO55 : 2; // 15:14 Defines pin-muxing selection for GPIO55
    Uint32 GPIO56 : 2; // 17:16 Defines pin-muxing selection for GPIO56
    Uint32 GPIO57 : 2; // 19:18 Defines pin-muxing selection for GPIO57
    Uint32 GPIO58 : 2; // 21:20 Defines pin-muxing selection for GPIO58
    Uint32 GPIO59 : 2; // 23:22 Defines pin-muxing selection for GPIO59
    Uint32 GPIO60 : 2; // 25:24 Defines pin-muxing selection for GPIO60
    Uint32 GPIO61 : 2; // 27:26 Defines pin-muxing selection for GPIO61
    Uint32 GPIO62 : 2; // 29:28 Defines pin-muxing selection for GPIO62
    Uint32 GPIO63 : 2; // 31:30 Defines pin-muxing selection for GPIO63
};

union GPBMUX2_REG
{
    Uint32 all;
    struct GPBMUX2_BITS bit;
};

struct GPBDIR_BITS
{                      // bits description
    Uint32 GPIO32 : 1; // 0 Defines direction for this pin in GPIO mode
    Uint32 GPIO33 : 1; // 1 Defines direction for this pin in GPIO mode
    Uint32 GPIO34 : 1; // 2 Defines direction for this pin in GPIO mode
    Uint32 GPIO35 : 1; // 3 Defines direction for this pin in GPIO mode
    Uint32 GPIO36 : 1; // 4 Defines direction for this pin in GPIO mode
    Uint32 GPIO37 : 1; // 5 Defines direction for this pin in GPIO mode
    Uint32 GPIO38 : 1; // 6 Defines direction for this pin in GPIO mode
    Uint32 GPIO39 : 1; // 7 Defines direction for this pin in GPIO mode
    Uint32 GPIO40 : 1; // 8 Defines direction for this pin in GPIO mode
    Uint32 GPIO41 : 1; // 9 Defines direction for this pin in GPIO mode
    Uint32 GPIO42 : 1; // 10 Defines direction for this pin in GPIO mode
    Uint32 GPIO43 : 1; // 11 Defines direction for this pin in GPIO mode
    Uint32 GPIO44 : 1; // 12 Defines direction for this pin in GPIO mode
    Uint32 GPIO45 : 1; // 13 Defines direction for this pin in GPIO mode
    Uint32 GPIO46 : 1; // 14 Defines direction for this pin in GPIO mode
    Uint32 GPIO47 : 1; // 15 Defines direction for this pin in GPIO mode
    Uint32 GPIO48 : 1; // 16 Defines direction for this pin in GPIO mode
    Uint32 GPIO49 : 1; // 17 Defines direction for this pin in GPIO mode
    Uint32 GPIO50 : 1; // 18 Defines direction for this pin in GPIO mode
    Uint32 GPIO51 : 1; // 19 Defines direction for this pin in GPIO mode
    Uint32 GPIO52 : 1; // 20 Defines direction for this pin in GPIO mode
    Uint32 GPIO53 : 1; // 21 Defines direction for this pin in GPIO mode
    Uint32 GPIO54 : 1; // 22 Defines direction for this pin in GPIO mode
    Uint32 GPIO55 : 1; // 23 Defines direction for this pin in GPIO mode
    Uint32 GPIO56 : 1; // 24 Defines direction for this pin in GPIO mode
    Uint32 GPIO57 : 1; // 25 Defines direction for this pin in GPIO mode
    Uint32 GPIO58 : 1; // 26 Defines direction for this pin in GPIO mode
    Uint32 GPIO59 : 1; // 27 Defines direction for this pin in GPIO mode
    Uint32 GPIO60 : 1; // 28 Defines direction for this pin in GPIO mode
    Uint32 GPIO61 : 1; // 29 Defines direction for this pin in GPIO mode
    Uint32 GPIO62 : 1; // 30 Defines direction for this pin in GPIO mode
    Uint32 GPIO63 : 1; // 31 Defines direction for this pin in GPIO mode
};

union GPBDIR_REG
{
    Uint32 all;
    struct GPBDIR_BITS bit;
};

struct GPBPUD_BITS
{                      // bits description
    Uint32 GPIO32 : 1; // 0 Pull-Up Disable control for this pin
    Uint32 GPIO33 : 1; // 1 Pull-Up Disable control for this pin
    Uint32 GPIO34 : 1; // 2 Pull-Up Disable control for this pin
    Uint32 GPIO35 : 1; // 3 Pull-Up Disable control for this pin
    Uint32 GPIO36 : 1; // 4 Pull-Up Disable control for this pin
    Uint32 GPIO37 : 1; // 5 Pull-Up Disable control for this pin
    Uint32 GPIO38 : 1; // 6 Pull-Up Disable control for this pin
    Uint32 GPIO39 : 1; // 7 Pull-Up Disable control for this pin
    Uint32 GPIO40 : 1; // 8 Pull-Up Disable control for this pin
    Uint32 GPIO41 : 1; // 9 Pull-Up Disable control for this pin
    Uint32 GPIO42 : 1; // 10 Pull-Up Disable control for this pin
    Uint32 GPIO43 : 1; // 11 Pull-Up Disable control for this pin
    Uint32 GPIO44 : 1; // 12 Pull-Up Disable control for this pin
    Uint32 GPIO45 : 1; // 13 Pull-Up Disable control for this pin
    Uint32 GPIO46 : 1; // 14 Pull-Up Disable control for this pin
    Uint32 GPIO47 : 1; // 15 Pull-Up Disable control for this pin
    Uint32 GPIO48 : 1; // 16 Pull-Up Disable control for this pin
    Uint32 GPIO49 : 1; // 17 Pull-Up Disable control for this pin
    Uint32 GPIO50 : 1; // 18 Pull-Up Disable control for this pin
    Uint32 GPIO51 : 1; // 19 Pull-Up Disable control for this pin
    Uint32 GPIO52 : 1; // 20 Pull-Up Disable control for this pin
    Uint32 GPIO53 : 1; // 21 Pull-Up Disable control for this pin
    Uint32 GPIO54 : 1; // 22 Pull-Up Disable control for this pin
    Uint32 GPIO55 : 1; // 23 Pull-Up Disable control for this pin
    Uint32 GPIO56 : 1; // 24 Pull-Up Disable control for this pin
    Uint32 GPIO57 : 1; // 25 Pull-Up Disable control for this pin
    Uint32 GPIO58 : 1; // 26 Pull-Up Disable control for this pin
    Uint32 GPIO59 : 1; // 27 Pull-Up Disable control for this pin
    Uint32 GPIO60 : 1; // 28 Pull-Up Disable control for this pin
    Uint32 GPIO61 : 1; // 29 Pull-Up Disable control for this pin
    Uint32 GPIO62 : 1; // 30 Pull-Up Disable control for this pin
    Uint32 GPIO63 : 1; // 31 Pull-Up Disable control for this pin
};

union GPBPUD_REG
{
    Uint32 all;
    struct GPBPUD_BITS bit;
};

struct GPBINV_BITS
{                      // bits description
    Uint32 GPIO32 : 1; // 0 Input inversion control for this pin
    Uint32 GPIO33 : 1; // 1 Input inversion control for this pin
    Uint32 GPIO34 : 1; // 2 Input inversion control for this pin
    Uint32 GPIO35 : 1; // 3 Input inversion control for this pin
    Uint32 GPIO36 : 1; // 4 Input inversion control for this pin
    Uint32 GPIO37 : 1; // 5 Input inversion control for this pin
    Uint32 GPIO38 : 1; // 6 Input inversion control for this pin
    Uint32 GPIO39 : 1; // 7 Input inversion control for this pin
    Uint32 GPIO40 : 1; // 8 Input inversion control for this pin
    Uint32 GPIO41 : 1; // 9 Input inversion control for this pin
    Uint32 GPIO42 : 1; // 10 Input inversion control for this pin
    Uint32 GPIO43 : 1; // 11 Input inversion control for this pin
    Uint32 GPIO44 : 1; // 12 Input inversion control for this pin
    Uint32 GPIO45 : 1; // 13 Input inversion control for this pin
    Uint32 GPIO46 : 1; // 14 Input inversion control for this pin
    Uint32 GPIO47 : 1; // 15 Input inversion control for this pin
    Uint32 GPIO48 : 1; // 16 Input inversion control for this pin
    Uint32 GPIO49 : 1; // 17 Input inversion control for this pin
    Uint32 GPIO50 : 1; // 18 Input inversion control for this pin
    Uint32 GPIO51 : 1; // 19 Input inversion control for this pin
    Uint32 GPIO52 : 1; // 20 Input inversion control for this pin
    Uint32 GPIO53 : 1; // 21 Input inversion control for this pin
    Uint32 GPIO54 : 1; // 22 Input inversion control for this pin
    Uint32 GPIO55 : 1; // 23 Input inversion control for this pin
    Uint32 GPIO56 : 1; // 24 Input inversion control for this pin
    Uint32 GPIO57 : 1; // 25 Input inversion control for this pin
    Uint32 GPIO58 : 1; // 26 Input inversion control for this pin
    Uint32 GPIO59 : 1; // 27 Input inversion control for this pin
    Uint32 GPIO60 : 1; // 28 Input inversion control for this pin
    Uint32 GPIO61 : 1; // 29 Input inversion control for this pin
    Uint32 GPIO62 : 1; // 30 Input inversion control for this pin
    Uint32 GPIO63 : 1; // 31 Input inversion control for this pin
};

union GPBINV_REG
{
    Uint32 all;
    struct GPBINV_BITS bit;
};

struct GPBODR_BITS
{                      // bits description
    Uint32 GPIO32 : 1; // 0 Output Open-Drain control for this pin
    Uint32 GPIO33 : 1; // 1 Output Open-Drain control for this pin
    Uint32 GPIO34 : 1; // 2 Output Open-Drain control for this pin
    Uint32 GPIO35 : 1; // 3 Output Open-Drain control for this pin
    Uint32 GPIO36 : 1; // 4 Output Open-Drain control for this pin
    Uint32 GPIO37 : 1; // 5 Output Open-Drain control for this pin
    Uint32 GPIO38 : 1; // 6 Output Open-Drain control for this pin
    Uint32 GPIO39 : 1; // 7 Output Open-Drain control for this pin
    Uint32 GPIO40 : 1; // 8 Output Open-Drain control for this pin
    Uint32 GPIO41 : 1; // 9 Output Open-Drain control for this pin
    Uint32 GPIO42 : 1; // 10 Output Open-Drain control for this pin
    Uint32 GPIO43 : 1; // 11 Output Open-Drain control for this pin
    Uint32 GPIO44 : 1; // 12 Output Open-Drain control for this pin
    Uint32 GPIO45 : 1; // 13 Output Open-Drain control for this pin
    Uint32 GPIO46 : 1; // 14 Output Open-Drain control for this pin
    Uint32 GPIO47 : 1; // 15 Output Open-Drain control for this pin
    Uint32 GPIO48 : 1; // 16 Output Open-Drain control for this pin
    Uint32 GPIO49 : 1; // 17 Output Open-Drain control for this pin
    Uint32 GPIO50 : 1; // 18 Output Open-Drain control for this pin
    Uint32 GPIO51 : 1; // 19 Output Open-Drain control for this pin
    Uint32 GPIO52 : 1; // 20 Output Open-Drain control for this pin
    Uint32 GPIO53 : 1; // 21 Output Open-Drain control for this pin
    Uint32 GPIO54 : 1; // 22 Output Open-Drain control for this pin
    Uint32 GPIO55 : 1; // 23 Output Open-Drain control for this pin
    Uint32 GPIO56 : 1; // 24 Output Open-Drain control for this pin
    Uint32 GPIO57 : 1; // 25 Output Open-Drain control for this pin
    Uint32 GPIO58 : 1; // 26 Output Open-Drain control for this pin
    Uint32 GPIO59 : 1; // 27 Output Open-Drain control for this pin
    Uint32 GPIO60 : 1; // 28 Output Open-Drain control for this pin
    Uint32 GPIO61 : 1; // 29 Output Open-Drain control for this pin
    Uint32 GPIO62 : 1; // 30 Output Open-Drain control for this pin
    Uint32 GPIO63 : 1; // 31 Output Open-Drain control for this pin
};

union GPBODR_REG
{
    Uint32 all;
    struct GPBODR_BITS bit;
};

struct GPBAMSEL_BITS
{                      // bits description
    Uint32 rsvd1  : 1; // 0 Reserved
    Uint32 rsvd2  : 1; // 1 Reserved
    Uint32 rsvd3  : 1; // 2 Reserved
    Uint32 rsvd4  : 1; // 3 Reserved
    Uint32 rsvd5  : 1; // 4 Reserved
    Uint32 rsvd6  : 1; // 5 Reserved
    Uint32 rsvd7  : 1; // 6 Reserved
    Uint32 rsvd8  : 1; // 7 Reserved
    Uint32 rsvd9  : 1; // 8 Reserved
    Uint32 rsvd10 : 1; // 9 Reserved
    Uint32 GPIO42 : 1; // 10 Analog Mode select for this pin
    Uint32 GPIO43 : 1; // 11 Analog Mode select for this pin
    Uint32 rsvd11 : 1; // 12 Reserved
    Uint32 rsvd12 : 1; // 13 Reserved
    Uint32 rsvd13 : 1; // 14 Reserved
    Uint32 rsvd14 : 1; // 15 Reserved
    Uint32 rsvd15 : 1; // 16 Reserved
    Uint32 rsvd16 : 1; // 17 Reserved
    Uint32 rsvd17 : 1; // 18 Reserved
    Uint32 rsvd18 : 1; // 19 Reserved
    Uint32 rsvd19 : 1; // 20 Reserved
    Uint32 rsvd20 : 1; // 21 Reserved
    Uint32 rsvd21 : 1; // 22 Reserved
    Uint32 rsvd22 : 1; // 23 Reserved
    Uint32 rsvd23 : 1; // 24 Reserved
    Uint32 rsvd24 : 1; // 25 Reserved
    Uint32 rsvd25 : 1; // 26 Reserved
    Uint32 rsvd26 : 1; // 27 Reserved
    Uint32 rsvd27 : 1; // 28 Reserved
    Uint32 rsvd28 : 1; // 29 Reserved
    Uint32 rsvd29 : 1; // 30 Reserved
    Uint32 rsvd30 : 1; // 31 Reserved
};

union GPBAMSEL_REG
{
    Uint32 all;
    struct GPBAMSEL_BITS bit;
};

struct GPBGMUX1_BITS
{                      // bits description
    Uint32 GPIO32 : 2; // 1:0 Defines pin-muxing selection for GPIO32
    Uint32 GPIO33 : 2; // 3:2 Defines pin-muxing selection for GPIO33
    Uint32 GPIO34 : 2; // 5:4 Defines pin-muxing selection for GPIO34
    Uint32 GPIO35 : 2; // 7:6 Defines pin-muxing selection for GPIO35
    Uint32 GPIO36 : 2; // 9:8 Defines pin-muxing selection for GPIO36
    Uint32 GPIO37 : 2; // 11:10 Defines pin-muxing selection for GPIO37
    Uint32 GPIO38 : 2; // 13:12 Defines pin-muxing selection for GPIO38
    Uint32 GPIO39 : 2; // 15:14 Defines pin-muxing selection for GPIO39
    Uint32 GPIO40 : 2; // 17:16 Defines pin-muxing selection for GPIO40
    Uint32 GPIO41 : 2; // 19:18 Defines pin-muxing selection for GPIO41
    Uint32 GPIO42 : 2; // 21:20 Defines pin-muxing selection for GPIO42
    Uint32 GPIO43 : 2; // 23:22 Defines pin-muxing selection for GPIO43
    Uint32 GPIO44 : 2; // 25:24 Defines pin-muxing selection for GPIO44
    Uint32 GPIO45 : 2; // 27:26 Defines pin-muxing selection for GPIO45
    Uint32 GPIO46 : 2; // 29:28 Defines pin-muxing selection for GPIO46
    Uint32 GPIO47 : 2; // 31:30 Defines pin-muxing selection for GPIO47
};

union GPBGMUX1_REG
{
    Uint32 all;
    struct GPBGMUX1_BITS bit;
};

struct GPBGMUX2_BITS
{                      // bits description
    Uint32 GPIO48 : 2; // 1:0 Defines pin-muxing selection for GPIO48
    Uint32 GPIO49 : 2; // 3:2 Defines pin-muxing selection for GPIO49
    Uint32 GPIO50 : 2; // 5:4 Defines pin-muxing selection for GPIO50
    Uint32 GPIO51 : 2; // 7:6 Defines pin-muxing selection for GPIO51
    Uint32 GPIO52 : 2; // 9:8 Defines pin-muxing selection for GPIO52
    Uint32 GPIO53 : 2; // 11:10 Defines pin-muxing selection for GPIO53
    Uint32 GPIO54 : 2; // 13:12 Defines pin-muxing selection for GPIO54
    Uint32 GPIO55 : 2; // 15:14 Defines pin-muxing selection for GPIO55
    Uint32 GPIO56 : 2; // 17:16 Defines pin-muxing selection for GPIO56
    Uint32 GPIO57 : 2; // 19:18 Defines pin-muxing selection for GPIO57
    Uint32 GPIO58 : 2; // 21:20 Defines pin-muxing selection for GPIO58
    Uint32 GPIO59 : 2; // 23:22 Defines pin-muxing selection for GPIO59
    Uint32 GPIO60 : 2; // 25:24 Defines pin-muxing selection for GPIO60
    Uint32 GPIO61 : 2; // 27:26 Defines pin-muxing selection for GPIO61
    Uint32 GPIO62 : 2; // 29:28 Defines pin-muxing selection for GPIO62
    Uint32 GPIO63 : 2; // 31:30 Defines pin-muxing selection for GPIO63
};

union GPBGMUX2_REG
{
    Uint32 all;
    struct GPBGMUX2_BITS bit;
};

struct GPBCSEL1_BITS
{                      // bits description
    Uint32 GPIO32 : 4; // 3:0 GPIO32 Controller CPU Select
    Uint32 GPIO33 : 4; // 7:4 GPIO33 Controller CPU Select
    Uint32 GPIO34 : 4; // 11:8 GPIO34 Controller CPU Select
    Uint32 GPIO35 : 4; // 15:12 GPIO35 Controller CPU Select
    Uint32 GPIO36 : 4; // 19:16 GPIO36 Controller CPU Select
    Uint32 GPIO37 : 4; // 23:20 GPIO37 Controller CPU Select
    Uint32 GPIO38 : 4; // 27:24 GPIO38 Controller CPU Select
    Uint32 GPIO39 : 4; // 31:28 GPIO39 Controller CPU Select
};

union GPBCSEL1_REG
{
    Uint32 all;
    struct GPBCSEL1_BITS bit;
};

struct GPBCSEL2_BITS
{                      // bits description
    Uint32 GPIO40 : 4; // 3:0 GPIO40 Controller CPU Select
    Uint32 GPIO41 : 4; // 7:4 GPIO41 Controller CPU Select
    Uint32 GPIO42 : 4; // 11:8 GPIO42 Controller CPU Select
    Uint32 GPIO43 : 4; // 15:12 GPIO43 Controller CPU Select
    Uint32 GPIO44 : 4; // 19:16 GPIO44 Controller CPU Select
    Uint32 GPIO45 : 4; // 23:20 GPIO45 Controller CPU Select
    Uint32 GPIO46 : 4; // 27:24 GPIO46 Controller CPU Select
    Uint32 GPIO47 : 4; // 31:28 GPIO47 Controller CPU Select
};

union GPBCSEL2_REG
{
    Uint32 all;
    struct GPBCSEL2_BITS bit;
};

struct GPBCSEL3_BITS
{                      // bits description
    Uint32 GPIO48 : 4; // 3:0 GPIO48 Controller CPU Select
    Uint32 GPIO49 : 4; // 7:4 GPIO49 Controller CPU Select
    Uint32 GPIO50 : 4; // 11:8 GPIO50 Controller CPU Select
    Uint32 GPIO51 : 4; // 15:12 GPIO51 Controller CPU Select
    Uint32 GPIO52 : 4; // 19:16 GPIO52 Controller CPU Select
    Uint32 GPIO53 : 4; // 23:20 GPIO53 Controller CPU Select
    Uint32 GPIO54 : 4; // 27:24 GPIO54 Controller CPU Select
    Uint32 GPIO55 : 4; // 31:28 GPIO55 Controller CPU Select
};

union GPBCSEL3_REG
{
    Uint32 all;
    struct GPBCSEL3_BITS bit;
};

struct GPBCSEL4_BITS
{                      // bits description
    Uint32 GPIO56 : 4; // 3:0 GPIO56 Controller CPU Select
    Uint32 GPIO57 : 4; // 7:4 GPIO57 Controller CPU Select
    Uint32 GPIO58 : 4; // 11:8 GPIO58 Controller CPU Select
    Uint32 GPIO59 : 4; // 15:12 GPIO59 Controller CPU Select
    Uint32 GPIO60 : 4; // 19:16 GPIO60 Controller CPU Select
    Uint32 GPIO61 : 4; // 23:20 GPIO61 Controller CPU Select
    Uint32 GPIO62 : 4; // 27:24 GPIO62 Controller CPU Select
    Uint32 GPIO63 : 4; // 31:28 GPIO63 Controller CPU Select
};

union GPBCSEL4_REG
{
    Uint32 all;
    struct GPBCSEL4_BITS bit;
};

struct GPBLOCK_BITS
{                      // bits description
    Uint32 GPIO32 : 1; // 0 Configuration Lock bit for this pin
    Uint32 GPIO33 : 1; // 1 Configuration Lock bit for this pin
    Uint32 GPIO34 : 1; // 2 Configuration Lock bit for this pin
    Uint32 GPIO35 : 1; // 3 Configuration Lock bit for this pin
    Uint32 GPIO36 : 1; // 4 Configuration Lock bit for this pin
    Uint32 GPIO37 : 1; // 5 Configuration Lock bit for this pin
    Uint32 GPIO38 : 1; // 6 Configuration Lock bit for this pin
    Uint32 GPIO39 : 1; // 7 Configuration Lock bit for this pin
    Uint32 GPIO40 : 1; // 8 Configuration Lock bit for this pin
    Uint32 GPIO41 : 1; // 9 Configuration Lock bit for this pin
    Uint32 GPIO42 : 1; // 10 Configuration Lock bit for this pin
    Uint32 GPIO43 : 1; // 11 Configuration Lock bit for this pin
    Uint32 GPIO44 : 1; // 12 Configuration Lock bit for this pin
    Uint32 GPIO45 : 1; // 13 Configuration Lock bit for this pin
    Uint32 GPIO46 : 1; // 14 Configuration Lock bit for this pin
    Uint32 GPIO47 : 1; // 15 Configuration Lock bit for this pin
    Uint32 GPIO48 : 1; // 16 Configuration Lock bit for this pin
    Uint32 GPIO49 : 1; // 17 Configuration Lock bit for this pin
    Uint32 GPIO50 : 1; // 18 Configuration Lock bit for this pin
    Uint32 GPIO51 : 1; // 19 Configuration Lock bit for this pin
    Uint32 GPIO52 : 1; // 20 Configuration Lock bit for this pin
    Uint32 GPIO53 : 1; // 21 Configuration Lock bit for this pin
    Uint32 GPIO54 : 1; // 22 Configuration Lock bit for this pin
    Uint32 GPIO55 : 1; // 23 Configuration Lock bit for this pin
    Uint32 GPIO56 : 1; // 24 Configuration Lock bit for this pin
    Uint32 GPIO57 : 1; // 25 Configuration Lock bit for this pin
    Uint32 GPIO58 : 1; // 26 Configuration Lock bit for this pin
    Uint32 GPIO59 : 1; // 27 Configuration Lock bit for this pin
    Uint32 GPIO60 : 1; // 28 Configuration Lock bit for this pin
    Uint32 GPIO61 : 1; // 29 Configuration Lock bit for this pin
    Uint32 GPIO62 : 1; // 30 Configuration Lock bit for this pin
    Uint32 GPIO63 : 1; // 31 Configuration Lock bit for this pin
};

union GPBLOCK_REG
{
    Uint32 all;
    struct GPBLOCK_BITS bit;
};

struct GPBCR_BITS
{                      // bits description
    Uint32 GPIO32 : 1; // 0 Configuration lock commit bit for this pin
    Uint32 GPIO33 : 1; // 1 Configuration lock commit bit for this pin
    Uint32 GPIO34 : 1; // 2 Configuration lock commit bit for this pin
    Uint32 GPIO35 : 1; // 3 Configuration lock commit bit for this pin
    Uint32 GPIO36 : 1; // 4 Configuration lock commit bit for this pin
    Uint32 GPIO37 : 1; // 5 Configuration lock commit bit for this pin
    Uint32 GPIO38 : 1; // 6 Configuration lock commit bit for this pin
    Uint32 GPIO39 : 1; // 7 Configuration lock commit bit for this pin
    Uint32 GPIO40 : 1; // 8 Configuration lock commit bit for this pin
    Uint32 GPIO41 : 1; // 9 Configuration lock commit bit for this pin
    Uint32 GPIO42 : 1; // 10 Configuration lock commit bit for this pin
    Uint32 GPIO43 : 1; // 11 Configuration lock commit bit for this pin
    Uint32 GPIO44 : 1; // 12 Configuration lock commit bit for this pin
    Uint32 GPIO45 : 1; // 13 Configuration lock commit bit for this pin
    Uint32 GPIO46 : 1; // 14 Configuration lock commit bit for this pin
    Uint32 GPIO47 : 1; // 15 Configuration lock commit bit for this pin
    Uint32 GPIO48 : 1; // 16 Configuration lock commit bit for this pin
    Uint32 GPIO49 : 1; // 17 Configuration lock commit bit for this pin
    Uint32 GPIO50 : 1; // 18 Configuration lock commit bit for this pin
    Uint32 GPIO51 : 1; // 19 Configuration lock commit bit for this pin
    Uint32 GPIO52 : 1; // 20 Configuration lock commit bit for this pin
    Uint32 GPIO53 : 1; // 21 Configuration lock commit bit for this pin
    Uint32 GPIO54 : 1; // 22 Configuration lock commit bit for this pin
    Uint32 GPIO55 : 1; // 23 Configuration lock commit bit for this pin
    Uint32 GPIO56 : 1; // 24 Configuration lock commit bit for this pin
    Uint32 GPIO57 : 1; // 25 Configuration lock commit bit for this pin
    Uint32 GPIO58 : 1; // 26 Configuration lock commit bit for this pin
    Uint32 GPIO59 : 1; // 27 Configuration lock commit bit for this pin
    Uint32 GPIO60 : 1; // 28 Configuration lock commit bit for this pin
    Uint32 GPIO61 : 1; // 29 Configuration lock commit bit for this pin
    Uint32 GPIO62 : 1; // 30 Configuration lock commit bit for this pin
    Uint32 GPIO63 : 1; // 31 Configuration lock commit bit for this pin
};

union GPBCR_REG
{
    Uint32 all;
    struct GPBCR_BITS bit;
};

struct GPCCTRL_BITS
{                        // bits description
    Uint32 QUALPRD0 : 8; // 7:0 Qualification sampling period for GPIO64 to GPIO71
    Uint32 QUALPRD1 : 8; // 15:8 Qualification sampling period for GPIO72 to GPIO79
    Uint32 QUALPRD2 : 8; // 23:16 Qualification sampling period for GPIO80 to GPIO87
    Uint32 QUALPRD3 : 8; // 31:24 Qualification sampling period for GPIO88 to GPIO94
};

union GPCCTRL_REG
{
    Uint32 all;
    struct GPCCTRL_BITS bit;
};

struct GPCQSEL1_BITS
{                      // bits description
    Uint32 GPIO64 : 2; // 1:0 Select input qualification type for GPIO64
    Uint32 GPIO65 : 2; // 3:2 Select input qualification type for GPIO65
    Uint32 GPIO66 : 2; // 5:4 Select input qualification type for GPIO66
    Uint32 GPIO67 : 2; // 7:6 Select input qualification type for GPIO67
    Uint32 GPIO68 : 2; // 9:8 Select input qualification type for GPIO68
    Uint32 GPIO69 : 2; // 11:10 Select input qualification type for GPIO69
    Uint32 GPIO70 : 2; // 13:12 Select input qualification type for GPIO70
    Uint32 GPIO71 : 2; // 15:14 Select input qualification type for GPIO71
    Uint32 GPIO72 : 2; // 17:16 Select input qualification type for GPIO72
    Uint32 GPIO73 : 2; // 19:18 Select input qualification type for GPIO73
    Uint32 GPIO74 : 2; // 21:20 Select input qualification type for GPIO74
    Uint32 GPIO75 : 2; // 23:22 Select input qualification type for GPIO75
    Uint32 GPIO76 : 2; // 25:24 Select input qualification type for GPIO76
    Uint32 GPIO77 : 2; // 27:26 Select input qualification type for GPIO77
    Uint32 GPIO78 : 2; // 29:28 Select input qualification type for GPIO78
    Uint32 GPIO79 : 2; // 31:30 Select input qualification type for GPIO79
};

union GPCQSEL1_REG
{
    Uint32 all;
    struct GPCQSEL1_BITS bit;
};

struct GPCQSEL2_BITS
{                      // bits description
    Uint32 GPIO80 : 2; // 1:0 Select input qualification type for GPIO80
    Uint32 GPIO81 : 2; // 3:2 Select input qualification type for GPIO81
    Uint32 GPIO82 : 2; // 5:4 Select input qualification type for GPIO82
    Uint32 GPIO83 : 2; // 7:6 Select input qualification type for GPIO83
    Uint32 GPIO84 : 2; // 9:8 Select input qualification type for GPIO84
    Uint32 GPIO85 : 2; // 11:10 Select input qualification type for GPIO85
    Uint32 GPIO86 : 2; // 13:12 Select input qualification type for GPIO86
    Uint32 GPIO87 : 2; // 15:14 Select input qualification type for GPIO87
    Uint32 GPIO88 : 2; // 17:16 Select input qualification type for GPIO88
    Uint32 GPIO89 : 2; // 19:18 Select input qualification type for GPIO89
    Uint32 GPIO90 : 2; // 21:20 Select input qualification type for GPIO90
    Uint32 GPIO91 : 2; // 23:22 Select input qualification type for GPIO91
    Uint32 GPIO92 : 2; // 25:24 Select input qualification type for GPIO92
    Uint32 GPIO93 : 2; // 27:26 Select input qualification type for GPIO93
    Uint32 GPIO94 : 2; // 29:28 Select input qualification type for GPIO94
    Uint32 rsvd1  : 2; // 31:30 Reserved
};

union GPCQSEL2_REG
{
    Uint32 all;
    struct GPCQSEL2_BITS bit;
};

struct GPCMUX1_BITS
{                      // bits description
    Uint32 GPIO64 : 2; // 1:0 Defines pin-muxing selection for GPIO64
    Uint32 GPIO65 : 2; // 3:2 Defines pin-muxing selection for GPIO65
    Uint32 GPIO66 : 2; // 5:4 Defines pin-muxing selection for GPIO66
    Uint32 GPIO67 : 2; // 7:6 Defines pin-muxing selection for GPIO67
    Uint32 GPIO68 : 2; // 9:8 Defines pin-muxing selection for GPIO68
    Uint32 GPIO69 : 2; // 11:10 Defines pin-muxing selection for GPIO69
    Uint32 GPIO70 : 2; // 13:12 Defines pin-muxing selection for GPIO70
    Uint32 GPIO71 : 2; // 15:14 Defines pin-muxing selection for GPIO71
    Uint32 GPIO72 : 2; // 17:16 Defines pin-muxing selection for GPIO72
    Uint32 GPIO73 : 2; // 19:18 Defines pin-muxing selection for GPIO73
    Uint32 GPIO74 : 2; // 21:20 Defines pin-muxing selection for GPIO74
    Uint32 GPIO75 : 2; // 23:22 Defines pin-muxing selection for GPIO75
    Uint32 GPIO76 : 2; // 25:24 Defines pin-muxing selection for GPIO76
    Uint32 GPIO77 : 2; // 27:26 Defines pin-muxing selection for GPIO77
    Uint32 GPIO78 : 2; // 29:28 Defines pin-muxing selection for GPIO78
    Uint32 GPIO79 : 2; // 31:30 Defines pin-muxing selection for GPIO79
};

union GPCMUX1_REG
{
    Uint32 all;
    struct GPCMUX1_BITS bit;
};

struct GPCMUX2_BITS
{                      // bits description
    Uint32 GPIO80 : 2; // 1:0 Defines pin-muxing selection for GPIO80
    Uint32 GPIO81 : 2; // 3:2 Defines pin-muxing selection for GPIO81
    Uint32 GPIO82 : 2; // 5:4 Defines pin-muxing selection for GPIO82
    Uint32 GPIO83 : 2; // 7:6 Defines pin-muxing selection for GPIO83
    Uint32 GPIO84 : 2; // 9:8 Defines pin-muxing selection for GPIO84
    Uint32 GPIO85 : 2; // 11:10 Defines pin-muxing selection for GPIO85
    Uint32 GPIO86 : 2; // 13:12 Defines pin-muxing selection for GPIO86
    Uint32 GPIO87 : 2; // 15:14 Defines pin-muxing selection for GPIO87
    Uint32 GPIO88 : 2; // 17:16 Defines pin-muxing selection for GPIO88
    Uint32 GPIO89 : 2; // 19:18 Defines pin-muxing selection for GPIO89
    Uint32 GPIO90 : 2; // 21:20 Defines pin-muxing selection for GPIO90
    Uint32 GPIO91 : 2; // 23:22 Defines pin-muxing selection for GPIO91
    Uint32 GPIO92 : 2; // 25:24 Defines pin-muxing selection for GPIO92
    Uint32 GPIO93 : 2; // 27:26 Defines pin-muxing selection for GPIO93
    Uint32 GPIO94 : 2; // 29:28 Defines pin-muxing selection for GPIO94
    Uint32 rsvd1  : 2; // 31:30 Reserved
};

union GPCMUX2_REG
{
    Uint32 all;
    struct GPCMUX2_BITS bit;
};

struct GPCDIR_BITS
{                      // bits description
    Uint32 GPIO64 : 1; // 0 Defines direction for this pin in GPIO mode
    Uint32 GPIO65 : 1; // 1 Defines direction for this pin in GPIO mode
    Uint32 GPIO66 : 1; // 2 Defines direction for this pin in GPIO mode
    Uint32 GPIO67 : 1; // 3 Defines direction for this pin in GPIO mode
    Uint32 GPIO68 : 1; // 4 Defines direction for this pin in GPIO mode
    Uint32 GPIO69 : 1; // 5 Defines direction for this pin in GPIO mode
    Uint32 GPIO70 : 1; // 6 Defines direction for this pin in GPIO mode
    Uint32 GPIO71 : 1; // 7 Defines direction for this pin in GPIO mode
    Uint32 GPIO72 : 1; // 8 Defines direction for this pin in GPIO mode
    Uint32 GPIO73 : 1; // 9 Defines direction for this pin in GPIO mode
    Uint32 GPIO74 : 1; // 10 Defines direction for this pin in GPIO mode
    Uint32 GPIO75 : 1; // 11 Defines direction for this pin in GPIO mode
    Uint32 GPIO76 : 1; // 12 Defines direction for this pin in GPIO mode
    Uint32 GPIO77 : 1; // 13 Defines direction for this pin in GPIO mode
    Uint32 GPIO78 : 1; // 14 Defines direction for this pin in GPIO mode
    Uint32 GPIO79 : 1; // 15 Defines direction for this pin in GPIO mode
    Uint32 GPIO80 : 1; // 16 Defines direction for this pin in GPIO mode
    Uint32 GPIO81 : 1; // 17 Defines direction for this pin in GPIO mode
    Uint32 GPIO82 : 1; // 18 Defines direction for this pin in GPIO mode
    Uint32 GPIO83 : 1; // 19 Defines direction for this pin in GPIO mode
    Uint32 GPIO84 : 1; // 20 Defines direction for this pin in GPIO mode
    Uint32 GPIO85 : 1; // 21 Defines direction for this pin in GPIO mode
    Uint32 GPIO86 : 1; // 22 Defines direction for this pin in GPIO mode
    Uint32 GPIO87 : 1; // 23 Defines direction for this pin in GPIO mode
    Uint32 GPIO88 : 1; // 24 Defines direction for this pin in GPIO mode
    Uint32 GPIO89 : 1; // 25 Defines direction for this pin in GPIO mode
    Uint32 GPIO90 : 1; // 26 Defines direction for this pin in GPIO mode
    Uint32 GPIO91 : 1; // 27 Defines direction for this pin in GPIO mode
    Uint32 GPIO92 : 1; // 28 Defines direction for this pin in GPIO mode
    Uint32 GPIO93 : 1; // 29 Defines direction for this pin in GPIO mode
    Uint32 GPIO94 : 1; // 30 Defines direction for this pin in GPIO mode
    Uint32 rsvd1  : 1; // 31 Reserved
};

union GPCDIR_REG
{
    Uint32 all;
    struct GPCDIR_BITS bit;
};

struct GPCPUD_BITS
{                      // bits description
    Uint32 GPIO64 : 1; // 0 Pull-Up Disable control for this pin
    Uint32 GPIO65 : 1; // 1 Pull-Up Disable control for this pin
    Uint32 GPIO66 : 1; // 2 Pull-Up Disable control for this pin
    Uint32 GPIO67 : 1; // 3 Pull-Up Disable control for this pin
    Uint32 GPIO68 : 1; // 4 Pull-Up Disable control for this pin
    Uint32 GPIO69 : 1; // 5 Pull-Up Disable control for this pin
    Uint32 GPIO70 : 1; // 6 Pull-Up Disable control for this pin
    Uint32 GPIO71 : 1; // 7 Pull-Up Disable control for this pin
    Uint32 GPIO72 : 1; // 8 Pull-Up Disable control for this pin
    Uint32 GPIO73 : 1; // 9 Pull-Up Disable control for this pin
    Uint32 GPIO74 : 1; // 10 Pull-Up Disable control for this pin
    Uint32 GPIO75 : 1; // 11 Pull-Up Disable control for this pin
    Uint32 GPIO76 : 1; // 12 Pull-Up Disable control for this pin
    Uint32 GPIO77 : 1; // 13 Pull-Up Disable control for this pin
    Uint32 GPIO78 : 1; // 14 Pull-Up Disable control for this pin
    Uint32 GPIO79 : 1; // 15 Pull-Up Disable control for this pin
    Uint32 GPIO80 : 1; // 16 Pull-Up Disable control for this pin
    Uint32 GPIO81 : 1; // 17 Pull-Up Disable control for this pin
    Uint32 GPIO82 : 1; // 18 Pull-Up Disable control for this pin
    Uint32 GPIO83 : 1; // 19 Pull-Up Disable control for this pin
    Uint32 GPIO84 : 1; // 20 Pull-Up Disable control for this pin
    Uint32 GPIO85 : 1; // 21 Pull-Up Disable control for this pin
    Uint32 GPIO86 : 1; // 22 Pull-Up Disable control for this pin
    Uint32 GPIO87 : 1; // 23 Pull-Up Disable control for this pin
    Uint32 GPIO88 : 1; // 24 Pull-Up Disable control for this pin
    Uint32 GPIO89 : 1; // 25 Pull-Up Disable control for this pin
    Uint32 GPIO90 : 1; // 26 Pull-Up Disable control for this pin
    Uint32 GPIO91 : 1; // 27 Pull-Up Disable control for this pin
    Uint32 GPIO92 : 1; // 28 Pull-Up Disable control for this pin
    Uint32 GPIO93 : 1; // 29 Pull-Up Disable control for this pin
    Uint32 GPIO94 : 1; // 30 Pull-Up Disable control for this pin
    Uint32 rsvd1  : 1; // 31 Reserved
};

union GPCPUD_REG
{
    Uint32 all;
    struct GPCPUD_BITS bit;
};

struct GPCINV_BITS
{                      // bits description
    Uint32 GPIO64 : 1; // 0 Input inversion control for this pin
    Uint32 GPIO65 : 1; // 1 Input inversion control for this pin
    Uint32 GPIO66 : 1; // 2 Input inversion control for this pin
    Uint32 GPIO67 : 1; // 3 Input inversion control for this pin
    Uint32 GPIO68 : 1; // 4 Input inversion control for this pin
    Uint32 GPIO69 : 1; // 5 Input inversion control for this pin
    Uint32 GPIO70 : 1; // 6 Input inversion control for this pin
    Uint32 GPIO71 : 1; // 7 Input inversion control for this pin
    Uint32 GPIO72 : 1; // 8 Input inversion control for this pin
    Uint32 GPIO73 : 1; // 9 Input inversion control for this pin
    Uint32 GPIO74 : 1; // 10 Input inversion control for this pin
    Uint32 GPIO75 : 1; // 11 Input inversion control for this pin
    Uint32 GPIO76 : 1; // 12 Input inversion control for this pin
    Uint32 GPIO77 : 1; // 13 Input inversion control for this pin
    Uint32 GPIO78 : 1; // 14 Input inversion control for this pin
    Uint32 GPIO79 : 1; // 15 Input inversion control for this pin
    Uint32 GPIO80 : 1; // 16 Input inversion control for this pin
    Uint32 GPIO81 : 1; // 17 Input inversion control for this pin
    Uint32 GPIO82 : 1; // 18 Input inversion control for this pin
    Uint32 GPIO83 : 1; // 19 Input inversion control for this pin
    Uint32 GPIO84 : 1; // 20 Input inversion control for this pin
    Uint32 GPIO85 : 1; // 21 Input inversion control for this pin
    Uint32 GPIO86 : 1; // 22 Input inversion control for this pin
    Uint32 GPIO87 : 1; // 23 Input inversion control for this pin
    Uint32 GPIO88 : 1; // 24 Input inversion control for this pin
    Uint32 GPIO89 : 1; // 25 Input inversion control for this pin
    Uint32 GPIO90 : 1; // 26 Input inversion control for this pin
    Uint32 GPIO91 : 1; // 27 Input inversion control for this pin
    Uint32 GPIO92 : 1; // 28 Input inversion control for this pin
    Uint32 GPIO93 : 1; // 29 Input inversion control for this pin
    Uint32 GPIO94 : 1; // 30 Input inversion control for this pin
    Uint32 rsvd1  : 1; // 31 Reserved
};

union GPCINV_REG
{
    Uint32 all;
    struct GPCINV_BITS bit;
};

struct GPCODR_BITS
{                      // bits description
    Uint32 GPIO64 : 1; // 0 Output Open-Drain control for this pin
    Uint32 GPIO65 : 1; // 1 Output Open-Drain control for this pin
    Uint32 GPIO66 : 1; // 2 Output Open-Drain control for this pin
    Uint32 GPIO67 : 1; // 3 Output Open-Drain control for this pin
    Uint32 GPIO68 : 1; // 4 Output Open-Drain control for this pin
    Uint32 GPIO69 : 1; // 5 Output Open-Drain control for this pin
    Uint32 GPIO70 : 1; // 6 Output Open-Drain control for this pin
    Uint32 GPIO71 : 1; // 7 Output Open-Drain control for this pin
    Uint32 GPIO72 : 1; // 8 Output Open-Drain control for this pin
    Uint32 GPIO73 : 1; // 9 Output Open-Drain control for this pin
    Uint32 GPIO74 : 1; // 10 Output Open-Drain control for this pin
    Uint32 GPIO75 : 1; // 11 Output Open-Drain control for this pin
    Uint32 GPIO76 : 1; // 12 Output Open-Drain control for this pin
    Uint32 GPIO77 : 1; // 13 Output Open-Drain control for this pin
    Uint32 GPIO78 : 1; // 14 Output Open-Drain control for this pin
    Uint32 GPIO79 : 1; // 15 Output Open-Drain control for this pin
    Uint32 GPIO80 : 1; // 16 Output Open-Drain control for this pin
    Uint32 GPIO81 : 1; // 17 Output Open-Drain control for this pin
    Uint32 GPIO82 : 1; // 18 Output Open-Drain control for this pin
    Uint32 GPIO83 : 1; // 19 Output Open-Drain control for this pin
    Uint32 GPIO84 : 1; // 20 Output Open-Drain control for this pin
    Uint32 GPIO85 : 1; // 21 Output Open-Drain control for this pin
    Uint32 GPIO86 : 1; // 22 Output Open-Drain control for this pin
    Uint32 GPIO87 : 1; // 23 Output Open-Drain control for this pin
    Uint32 GPIO88 : 1; // 24 Output Open-Drain control for this pin
    Uint32 GPIO89 : 1; // 25 Output Open-Drain control for this pin
    Uint32 GPIO90 : 1; // 26 Output Open-Drain control for this pin
    Uint32 GPIO91 : 1; // 27 Output Open-Drain control for this pin
    Uint32 GPIO92 : 1; // 28 Output Open-Drain control for this pin
    Uint32 GPIO93 : 1; // 29 Output Open-Drain control for this pin
    Uint32 GPIO94 : 1; // 30 Output Open-Drain control for this pin
    Uint32 rsvd1  : 1; // 31 Reserved
};

union GPCODR_REG
{
    Uint32 all;
    struct GPCODR_BITS bit;
};

struct GPCGMUX1_BITS
{                      // bits description
    Uint32 GPIO64 : 2; // 1:0 Defines pin-muxing selection for GPIO64
    Uint32 GPIO65 : 2; // 3:2 Defines pin-muxing selection for GPIO65
    Uint32 GPIO66 : 2; // 5:4 Defines pin-muxing selection for GPIO66
    Uint32 GPIO67 : 2; // 7:6 Defines pin-muxing selection for GPIO67
    Uint32 GPIO68 : 2; // 9:8 Defines pin-muxing selection for GPIO68
    Uint32 GPIO69 : 2; // 11:10 Defines pin-muxing selection for GPIO69
    Uint32 GPIO70 : 2; // 13:12 Defines pin-muxing selection for GPIO70
    Uint32 GPIO71 : 2; // 15:14 Defines pin-muxing selection for GPIO71
    Uint32 GPIO72 : 2; // 17:16 Defines pin-muxing selection for GPIO72
    Uint32 GPIO73 : 2; // 19:18 Defines pin-muxing selection for GPIO73
    Uint32 GPIO74 : 2; // 21:20 Defines pin-muxing selection for GPIO74
    Uint32 GPIO75 : 2; // 23:22 Defines pin-muxing selection for GPIO75
    Uint32 GPIO76 : 2; // 25:24 Defines pin-muxing selection for GPIO76
    Uint32 GPIO77 : 2; // 27:26 Defines pin-muxing selection for GPIO77
    Uint32 GPIO78 : 2; // 29:28 Defines pin-muxing selection for GPIO78
    Uint32 GPIO79 : 2; // 31:30 Defines pin-muxing selection for GPIO79
};

union GPCGMUX1_REG
{
    Uint32 all;
    struct GPCGMUX1_BITS bit;
};

struct GPCGMUX2_BITS
{                      // bits description
    Uint32 GPIO80 : 2; // 1:0 Defines pin-muxing selection for GPIO80
    Uint32 GPIO81 : 2; // 3:2 Defines pin-muxing selection for GPIO81
    Uint32 GPIO82 : 2; // 5:4 Defines pin-muxing selection for GPIO82
    Uint32 GPIO83 : 2; // 7:6 Defines pin-muxing selection for GPIO83
    Uint32 GPIO84 : 2; // 9:8 Defines pin-muxing selection for GPIO84
    Uint32 GPIO85 : 2; // 11:10 Defines pin-muxing selection for GPIO85
    Uint32 GPIO86 : 2; // 13:12 Defines pin-muxing selection for GPIO86
    Uint32 GPIO87 : 2; // 15:14 Defines pin-muxing selection for GPIO87
    Uint32 GPIO88 : 2; // 17:16 Defines pin-muxing selection for GPIO88
    Uint32 GPIO89 : 2; // 19:18 Defines pin-muxing selection for GPIO89
    Uint32 GPIO90 : 2; // 21:20 Defines pin-muxing selection for GPIO90
    Uint32 GPIO91 : 2; // 23:22 Defines pin-muxing selection for GPIO91
    Uint32 GPIO92 : 2; // 25:24 Defines pin-muxing selection for GPIO92
    Uint32 GPIO93 : 2; // 27:26 Defines pin-muxing selection for GPIO93
    Uint32 GPIO94 : 2; // 29:28 Defines pin-muxing selection for GPIO94
    Uint32 rsvd1  : 2; // 31:30 Reserved
};

union GPCGMUX2_REG
{
    Uint32 all;
    struct GPCGMUX2_BITS bit;
};

struct GPCCSEL1_BITS
{                      // bits description
    Uint32 GPIO64 : 4; // 3:0 GPIO64 Controller CPU Select
    Uint32 GPIO65 : 4; // 7:4 GPIO65 Controller CPU Select
    Uint32 GPIO66 : 4; // 11:8 GPIO66 Controller CPU Select
    Uint32 GPIO67 : 4; // 15:12 GPIO67 Controller CPU Select
    Uint32 GPIO68 : 4; // 19:16 GPIO68 Controller CPU Select
    Uint32 GPIO69 : 4; // 23:20 GPIO69 Controller CPU Select
    Uint32 GPIO70 : 4; // 27:24 GPIO70 Controller CPU Select
    Uint32 GPIO71 : 4; // 31:28 GPIO71 Controller CPU Select
};

union GPCCSEL1_REG
{
    Uint32 all;
    struct GPCCSEL1_BITS bit;
};

struct GPCCSEL2_BITS
{                      // bits description
    Uint32 GPIO72 : 4; // 3:0 GPIO72 Controller CPU Select
    Uint32 GPIO73 : 4; // 7:4 GPIO73 Controller CPU Select
    Uint32 GPIO74 : 4; // 11:8 GPIO74 Controller CPU Select
    Uint32 GPIO75 : 4; // 15:12 GPIO75 Controller CPU Select
    Uint32 GPIO76 : 4; // 19:16 GPIO76 Controller CPU Select
    Uint32 GPIO77 : 4; // 23:20 GPIO77 Controller CPU Select
    Uint32 GPIO78 : 4; // 27:24 GPIO78 Controller CPU Select
    Uint32 GPIO79 : 4; // 31:28 GPIO79 Controller CPU Select
};

union GPCCSEL2_REG
{
    Uint32 all;
    struct GPCCSEL2_BITS bit;
};

struct GPCCSEL3_BITS
{                      // bits description
    Uint32 GPIO80 : 4; // 3:0 GPIO80 Controller CPU Select
    Uint32 GPIO81 : 4; // 7:4 GPIO81 Controller CPU Select
    Uint32 GPIO82 : 4; // 11:8 GPIO82 Controller CPU Select
    Uint32 GPIO83 : 4; // 15:12 GPIO83 Controller CPU Select
    Uint32 GPIO84 : 4; // 19:16 GPIO84 Controller CPU Select
    Uint32 GPIO85 : 4; // 23:20 GPIO85 Controller CPU Select
    Uint32 GPIO86 : 4; // 27:24 GPIO86 Controller CPU Select
    Uint32 GPIO87 : 4; // 31:28 GPIO87 Controller CPU Select
};

union GPCCSEL3_REG
{
    Uint32 all;
    struct GPCCSEL3_BITS bit;
};

struct GPCCSEL4_BITS
{                      // bits description
    Uint32 GPIO88 : 4; // 3:0 GPIO88 Controller CPU Select
    Uint32 GPIO89 : 4; // 7:4 GPIO89 Controller CPU Select
    Uint32 GPIO90 : 4; // 11:8 GPIO90 Controller CPU Select
    Uint32 GPIO91 : 4; // 15:12 GPIO91 Controller CPU Select
    Uint32 GPIO92 : 4; // 19:16 GPIO92 Controller CPU Select
    Uint32 GPIO93 : 4; // 23:20 GPIO93 Controller CPU Select
    Uint32 GPIO94 : 4; // 27:24 GPIO94 Controller CPU Select
    Uint32 rsvd1  : 4; // 31:28 Reserved
};

union GPCCSEL4_REG
{
    Uint32 all;
    struct GPCCSEL4_BITS bit;
};

struct GPCLOCK_BITS
{                      // bits description
    Uint32 GPIO64 : 1; // 0 Configuration Lock bit for this pin
    Uint32 GPIO65 : 1; // 1 Configuration Lock bit for this pin
    Uint32 GPIO66 : 1; // 2 Configuration Lock bit for this pin
    Uint32 GPIO67 : 1; // 3 Configuration Lock bit for this pin
    Uint32 GPIO68 : 1; // 4 Configuration Lock bit for this pin
    Uint32 GPIO69 : 1; // 5 Configuration Lock bit for this pin
    Uint32 GPIO70 : 1; // 6 Configuration Lock bit for this pin
    Uint32 GPIO71 : 1; // 7 Configuration Lock bit for this pin
    Uint32 GPIO72 : 1; // 8 Configuration Lock bit for this pin
    Uint32 GPIO73 : 1; // 9 Configuration Lock bit for this pin
    Uint32 GPIO74 : 1; // 10 Configuration Lock bit for this pin
    Uint32 GPIO75 : 1; // 11 Configuration Lock bit for this pin
    Uint32 GPIO76 : 1; // 12 Configuration Lock bit for this pin
    Uint32 GPIO77 : 1; // 13 Configuration Lock bit for this pin
    Uint32 GPIO78 : 1; // 14 Configuration Lock bit for this pin
    Uint32 GPIO79 : 1; // 15 Configuration Lock bit for this pin
    Uint32 GPIO80 : 1; // 16 Configuration Lock bit for this pin
    Uint32 GPIO81 : 1; // 17 Configuration Lock bit for this pin
    Uint32 GPIO82 : 1; // 18 Configuration Lock bit for this pin
    Uint32 GPIO83 : 1; // 19 Configuration Lock bit for this pin
    Uint32 GPIO84 : 1; // 20 Configuration Lock bit for this pin
    Uint32 GPIO85 : 1; // 21 Configuration Lock bit for this pin
    Uint32 GPIO86 : 1; // 22 Configuration Lock bit for this pin
    Uint32 GPIO87 : 1; // 23 Configuration Lock bit for this pin
    Uint32 GPIO88 : 1; // 24 Configuration Lock bit for this pin
    Uint32 GPIO89 : 1; // 25 Configuration Lock bit for this pin
    Uint32 GPIO90 : 1; // 26 Configuration Lock bit for this pin
    Uint32 GPIO91 : 1; // 27 Configuration Lock bit for this pin
    Uint32 GPIO92 : 1; // 28 Configuration Lock bit for this pin
    Uint32 GPIO93 : 1; // 29 Configuration Lock bit for this pin
    Uint32 GPIO94 : 1; // 30 Configuration Lock bit for this pin
    Uint32 rsvd1  : 1; // 31 Reserved
};

union GPCLOCK_REG
{
    Uint32 all;
    struct GPCLOCK_BITS bit;
};

struct GPCCR_BITS
{                      // bits description
    Uint32 GPIO64 : 1; // 0 Configuration lock commit bit for this pin
    Uint32 GPIO65 : 1; // 1 Configuration lock commit bit for this pin
    Uint32 GPIO66 : 1; // 2 Configuration lock commit bit for this pin
    Uint32 GPIO67 : 1; // 3 Configuration lock commit bit for this pin
    Uint32 GPIO68 : 1; // 4 Configuration lock commit bit for this pin
    Uint32 GPIO69 : 1; // 5 Configuration lock commit bit for this pin
    Uint32 GPIO70 : 1; // 6 Configuration lock commit bit for this pin
    Uint32 GPIO71 : 1; // 7 Configuration lock commit bit for this pin
    Uint32 GPIO72 : 1; // 8 Configuration lock commit bit for this pin
    Uint32 GPIO73 : 1; // 9 Configuration lock commit bit for this pin
    Uint32 GPIO74 : 1; // 10 Configuration lock commit bit for this pin
    Uint32 GPIO75 : 1; // 11 Configuration lock commit bit for this pin
    Uint32 GPIO76 : 1; // 12 Configuration lock commit bit for this pin
    Uint32 GPIO77 : 1; // 13 Configuration lock commit bit for this pin
    Uint32 GPIO78 : 1; // 14 Configuration lock commit bit for this pin
    Uint32 GPIO79 : 1; // 15 Configuration lock commit bit for this pin
    Uint32 GPIO80 : 1; // 16 Configuration lock commit bit for this pin
    Uint32 GPIO81 : 1; // 17 Configuration lock commit bit for this pin
    Uint32 GPIO82 : 1; // 18 Configuration lock commit bit for this pin
    Uint32 GPIO83 : 1; // 19 Configuration lock commit bit for this pin
    Uint32 GPIO84 : 1; // 20 Configuration lock commit bit for this pin
    Uint32 GPIO85 : 1; // 21 Configuration lock commit bit for this pin
    Uint32 GPIO86 : 1; // 22 Configuration lock commit bit for this pin
    Uint32 GPIO87 : 1; // 23 Configuration lock commit bit for this pin
    Uint32 GPIO88 : 1; // 24 Configuration lock commit bit for this pin
    Uint32 GPIO89 : 1; // 25 Configuration lock commit bit for this pin
    Uint32 GPIO90 : 1; // 26 Configuration lock commit bit for this pin
    Uint32 GPIO91 : 1; // 27 Configuration lock commit bit for this pin
    Uint32 GPIO92 : 1; // 28 Configuration lock commit bit for this pin
    Uint32 GPIO93 : 1; // 29 Configuration lock commit bit for this pin
    Uint32 GPIO94 : 1; // 30 Configuration lock commit bit for this pin
    Uint32 rsvd1  : 1; // 31 Reserved
};

union GPCCR_REG
{
    Uint32 all;
    struct GPCCR_BITS bit;
};

struct GPDCTRL_BITS
{                        // bits description
    Uint32 QUALPRD0 : 8; // 7:0 Qualification sampling period for GPIO96 to GPIO103
    Uint32 QUALPRD1 : 8; // 15:8 Qualification sampling period for GPIO104 to GPIO111
};

union GPDCTRL_REG
{
    Uint32 all;
    struct GPDCTRL_BITS bit;
};

struct GPDQSEL1_BITS
{                       // bits description
    Uint32 rsvd1   : 6; // 5:0 Reserved
    Uint32 GPIO99  : 2; // 7:6 Select input qualification type for GPIO99
    Uint32 GPIO100 : 2; // 9:8 Select input qualification type for GPIO100
    Uint32 rsvd2   : 4; // 13:10 Reserved
    Uint32 GPIO103 : 2; // 15:14 Select input qualification type for GPIO103
    Uint32 GPIO104 : 2; // 17:16 Select input qualification type for GPIO104
    Uint32 GPIO105 : 2; // 19:18 Select input qualification type for GPIO105
    Uint32 GPIO106 : 2; // 21:20 Select input qualification type for GPIO106
};

union GPDQSEL1_REG
{
    Uint32 all;
    struct GPDQSEL1_BITS bit;
};

struct GPDQSEL2_BITS
{ // bits description
    Uint32 rsvd1 : 32;
};

union GPDQSEL2_REG
{
    Uint32 all;
    struct GPDQSEL2_BITS bit;
};

struct GPDMUX1_BITS
{                       // bits description
    Uint32 rsvd1   : 6; // 5:0 Reserved
    Uint32 GPIO99  : 2; // 7:6 Defines pin-muxing selection for GPIO99
    Uint32 GPIO100 : 2; // 9:8 Defines pin-muxing selection for GPIO100
    Uint32 rsvd2   : 4; // 13:10 Reserved
    Uint32 GPIO103 : 2; // 15:14 Defines pin-muxing selection for GPIO103
    Uint32 GPIO104 : 2; // 17:16 Defines pin-muxing selection for GPIO104
    Uint32 GPIO105 : 2; // 19:18 Defines pin-muxing selection for GPIO105
    Uint32 GPIO106 : 2; // 21:20 Defines pin-muxing selection for GPIO106
};

union GPDMUX1_REG
{
    Uint32 all;
    struct GPDMUX1_BITS bit;
};

struct GPDMUX2_BITS
{ // bits description
    Uint32 rsvd1 : 32;
};

union GPDMUX2_REG
{
    Uint32 all;
    struct GPDMUX2_BITS bit;
};

struct GPDDIR_BITS
{                       // bits description
    Uint32 rsvd1   : 3; // 2:0 Reserved
    Uint32 GPIO99  : 1; // 3 Defines direction for this pin in GPIO mode
    Uint32 GPIO100 : 1; // 4 Defines direction for this pin in GPIO mode
    Uint32 rsvd2   : 2; // 6:5 Reserved
    Uint32 GPIO103 : 1; // 7 Defines direction for this pin in GPIO mode
    Uint32 GPIO104 : 1; // 8 Defines direction for this pin in GPIO mode
    Uint32 GPIO105 : 1; // 9 Defines direction for this pin in GPIO mode
    Uint32 GPIO106 : 1; // 10 Defines direction for this pin in GPIO mode
};

union GPDDIR_REG
{
    Uint32 all;
    struct GPDDIR_BITS bit;
};

struct GPDPUD_BITS
{                       // bits description
    Uint32 rsvd1   : 3; // 2:0 Reserved
    Uint32 GPIO99  : 1; // 3 Pull-Up Disable control for this pin
    Uint32 GPIO100 : 1; // 4 Pull-Up Disable control for this pin
    Uint32 rsvd2   : 2; // 6:5 Reserved
    Uint32 GPIO103 : 1; // 7 Pull-Up Disable control for this pin
    Uint32 GPIO104 : 1; // 8 Pull-Up Disable control for this pin
    Uint32 GPIO105 : 1; // 9 Pull-Up Disable control for this pin
    Uint32 GPIO106 : 1; // 10 Pull-Up Disable control for this pin
};

union GPDPUD_REG
{
    Uint32 all;
    struct GPDPUD_BITS bit;
};

struct GPDINV_BITS
{                       // bits description
    Uint32 rsvd1   : 3; // 2:0 Reserved
    Uint32 GPIO99  : 1; // 3 Input inversion control for this pin
    Uint32 GPIO100 : 1; // 4 Input inversion control for this pin
    Uint32 rsvd2   : 2; // 6:5 Reserved
    Uint32 GPIO103 : 1; // 7 Input inversion control for this pin
    Uint32 GPIO104 : 1; // 8 Input inversion control for this pin
    Uint32 GPIO105 : 1; // 9 Input inversion control for this pin
    Uint32 GPIO106 : 1; // 10 Input inversion control for this pin
};

union GPDINV_REG
{
    Uint32 all;
    struct GPDINV_BITS bit;
};

struct GPDODR_BITS
{                       // bits description
    Uint32 rsvd1   : 3; // 2:0 Reserved
    Uint32 GPIO99  : 1; // 3 Output Open-Drain control for this pin
    Uint32 GPIO100 : 1; // 4 Output Open-Drain control for this pin
    Uint32 rsvd2   : 2; // 6:5 Reserved
    Uint32 GPIO103 : 1; // 7 Output Open-Drain control for this pin
    Uint32 GPIO104 : 1; // 8 Output Open-Drain control for this pin
    Uint32 GPIO105 : 1; // 9 Output Open-Drain control for this pin
    Uint32 GPIO106 : 1; // 10 Output Open-Drain control for this pin
};

union GPDODR_REG
{
    Uint32 all;
    struct GPDODR_BITS bit;
};

struct GPDGMUX1_BITS
{                       // bits description
    Uint32 rsvd1   : 6; // 5:0 Reserved
    Uint32 GPIO99  : 2; // 7:6 Defines pin-muxing selection for GPIO99
    Uint32 GPIO100 : 2; // 9:8 Defines pin-muxing selection for GPIO100
    Uint32 rsvd2   : 4; // 13:10 Reserved
    Uint32 GPIO103 : 2; // 15:14 Defines pin-muxing selection for GPIO103
    Uint32 GPIO104 : 2; // 17:16 Defines pin-muxing selection for GPIO104
    Uint32 GPIO105 : 2; // 19:18 Defines pin-muxing selection for GPIO105
    Uint32 GPIO106 : 2; // 21:20 Defines pin-muxing selection for GPIO106
};

union GPDGMUX1_REG
{
    Uint32 all;
    struct GPDGMUX1_BITS bit;
};

struct GPDGMUX2_BITS
{ // bits description
    Uint32 rsvd1 : 32;
};

union GPDGMUX2_REG
{
    Uint32 all;
    struct GPDGMUX2_BITS bit;
};

struct GPDCSEL1_BITS
{                        // bits description
    Uint32 rsvd1   : 12; // 11:0 Reserved
    Uint32 GPIO99  : 4;  // 15:12 GPIO99 Controller CPU Select
    Uint32 GPIO100 : 4;  // 19:16 GPIO100 Controller CPU Select
    Uint32 rsvd2   : 8;  // 27:20 Reserved
    Uint32 GPIO103 : 4;  // 31:28 GPIO103 Controller CPU Select
};

union GPDCSEL1_REG
{
    Uint32 all;
    struct GPDCSEL1_BITS bit;
};

struct GPDCSEL2_BITS
{                       // bits description
    Uint32 GPIO104 : 4; // 3:0 GPIO104 Controller CPU Select
    Uint32 GPIO105 : 4; // 7:4 GPIO105 Controller CPU Select
    Uint32 GPIO106 : 4; // 11:8 GPIO106 Controller CPU Select
};

union GPDCSEL2_REG
{
    Uint32 all;
    struct GPDCSEL2_BITS bit;
};

struct GPDCSEL3_BITS
{ // bits description
    Uint32 rsvd1 : 32;
};

union GPDCSEL3_REG
{
    Uint32 all;
    struct GPDCSEL3_BITS bit;
};

struct GPDCSEL4_BITS
{ // bits description
    Uint32 rsvd1 : 32;
};

union GPDCSEL4_REG
{
    Uint32 all;
    struct GPDCSEL4_BITS bit;
};

struct GPDLOCK_BITS
{                       // bits description
    Uint32 rsvd1   : 3; // 2:0 Reserved
    Uint32 GPIO99  : 1; // 3 Configuration Lock bit for this pin
    Uint32 GPIO100 : 1; // 4 Configuration Lock bit for this pin
    Uint32 rvsd2   : 2; // 6:5 Reserved
    Uint32 GPIO103 : 1; // 7 Configuration Lock bit for this pin
    Uint32 GPIO104 : 1; // 8 Configuration Lock bit for this pin
    Uint32 GPIO105 : 1; // 9 Configuration Lock bit for this pin
    Uint32 GPIO106 : 1; // 10 Configuration Lock bit for this pin
};

union GPDLOCK_REG
{
    Uint32 all;
    struct GPDLOCK_BITS bit;
};

struct GPDCR_BITS
{                       // bits description
    Uint32 rsvd1   : 3; // 2:0 Reserved
    Uint32 GPIO99  : 1; // 3 Configuration lock commit bit for this pin
    Uint32 GPIO100 : 1; // 4 Configuration lock commit bit for this pin
    Uint32 rvsd2   : 2; // 6:5 Reserved
    Uint32 GPIO103 : 1; // 7 Configuration lock commit bit for this pin
    Uint32 GPIO104 : 1; // 8 Configuration lock commit bit for this pin
    Uint32 GPIO105 : 1; // 9 Configuration lock commit bit for this pin
    Uint32 GPIO106 : 1; // 10 Configuration lock commit bit for this pin
};

union GPDCR_REG
{
    Uint32 all;
    struct GPDCR_BITS bit;
};

struct GPECTRL_BITS
{                        // bits description
    Uint32 QUALPRD0 : 8; // 7:0 Qualification sampling period for GPIO128 to GPIO135
};

union GPECTRL_REG
{
    Uint32 all;
    struct GPECTRL_BITS bit;
};

struct GPEQSEL1_BITS
{                        // bits description
    Uint32 rsvd1   : 10; // 9:0 Reserved
    Uint32 GPIO133 : 2;  // 11:10 Select input qualification type for GPIO133
};

union GPEQSEL1_REG
{
    Uint32 all;
    struct GPEQSEL1_BITS bit;
};

struct GPEQSEL2_BITS
{ // bits description
    Uint32 rsvd1 : 32;
};

union GPEQSEL2_REG
{
    Uint32 all;
    struct GPEQSEL2_BITS bit;
};

struct GPEMUX1_BITS
{                        // bits description
    Uint32 rsvd1   : 10; // 9:0 Reserved
    Uint32 GPIO133 : 2;  // 11:10 Defines pin-muxing selection for GPIO133
};

union GPEMUX1_REG
{
    Uint32 all;
    struct GPEMUX1_BITS bit;
};

struct GPEMUX2_BITS
{ // bits description
    Uint32 rsvd1 : 32;
};

union GPEMUX2_REG
{
    Uint32 all;
    struct GPEMUX2_BITS bit;
};

struct GPEDIR_BITS
{                       // bits description
    Uint32 rsvd1   : 5; // 4:0 Reserved
    Uint32 GPIO133 : 1; // 5 Defines direction for this pin in GPIO mode
};

union GPEDIR_REG
{
    Uint32 all;
    struct GPEDIR_BITS bit;
};

struct GPEPUD_BITS
{                       // bits description
    Uint32 rsvd1   : 5; // 4:0 Reserved
    Uint32 GPIO133 : 1; // 5 Pull-Up Disable control for this pin
};

union GPEPUD_REG
{
    Uint32 all;
    struct GPEPUD_BITS bit;
};

struct GPEINV_BITS
{                       // bits description
    Uint32 rsvd1   : 5; // 4:0 Reserved
    Uint32 GPIO133 : 1; // 5 Input inversion control for this pin
};

union GPEINV_REG
{
    Uint32 all;
    struct GPEINV_BITS bit;
};

struct GPEODR_BITS
{                       // bits description
    Uint32 rsvd1   : 5; // 4:0 Reserved
    Uint32 GPIO133 : 1; // 5 Output Open-Drain control for this pin
};

union GPEODR_REG
{
    Uint32 all;
    struct GPEODR_BITS bit;
};

struct GPEGMUX1_BITS
{                        // bits description
    Uint32 rsvd1   : 10; // 9:0 Reserved
    Uint32 GPIO133 : 2;  // 11:10 Defines pin-muxing selection for GPIO133
};

union GPEGMUX1_REG
{
    Uint32 all;
    struct GPEGMUX1_BITS bit;
};

struct GPEGMUX2_BITS
{ // bits description
    Uint32 rsvd1 : 32;
};

union GPEGMUX2_REG
{
    Uint32 all;
    struct GPEGMUX2_BITS bit;
};

struct GPECSEL1_BITS
{                        // bits description
    Uint32 GPIO128 : 20; // 19:0 Reserved
    Uint32 GPIO133 : 4;  // 23:20 GPIO133 Controller CPU Select
};

union GPECSEL1_REG
{
    Uint32 all;
    struct GPECSEL1_BITS bit;
};

struct GPECSEL2_BITS
{ // bits description
    Uint32 rsvd1 : 32;
};

union GPECSEL2_REG
{
    Uint32 all;
    struct GPECSEL2_BITS bit;
};

struct GPECSEL3_BITS
{ // bits description
    Uint32 rsvd1 : 32;
};

union GPECSEL3_REG
{
    Uint32 all;
    struct GPECSEL3_BITS bit;
};

struct GPECSEL4_BITS
{ // bits description
    Uint32 rsvd1 : 32;
};

union GPECSEL4_REG
{
    Uint32 all;
    struct GPECSEL4_BITS bit;
};

struct GPELOCK_BITS
{                       // bits description
    Uint32 rsvd1   : 5; // 4:0 Reserved
    Uint32 GPIO133 : 1; // 5 Configuration Lock bit for this pin
};

union GPELOCK_REG
{
    Uint32 all;
    struct GPELOCK_BITS bit;
};

struct GPECR_BITS
{                       // bits description
    Uint32 rsvd1   : 5; // 4:0 Reserved
    Uint32 GPIO133 : 1; // 5 Configuration lock commit bit for this pin
};

union GPECR_REG
{
    Uint32 all;
    struct GPECR_BITS bit;
};

struct GPFCTRL_BITS
{ // bits description
    Uint32 rsvd1 : 32;
};

union GPFCTRL_REG
{
    Uint32 all;
    struct GPFCTRL_BITS bit;
};

struct GPFQSEL1_BITS
{ // bits description
    Uint32 rsvd1 : 32;
};

union GPFQSEL1_REG
{
    Uint32 all;
    struct GPFQSEL1_BITS bit;
};

struct GPFMUX1_BITS
{ // bits description
    Uint32 rsvd1 : 32;
};

union GPFMUX1_REG
{
    Uint32 all;
    struct GPFMUX1_BITS bit;
};

struct GPFDIR_BITS
{ // bits description
    Uint32 rsvd1 : 32;
};

union GPFDIR_REG
{
    Uint32 all;
    struct GPFDIR_BITS bit;
};

struct GPFPUD_BITS
{ // bits description
    Uint32 rsvd1 : 32;
};

union GPFPUD_REG
{
    Uint32 all;
    struct GPFPUD_BITS bit;
};

struct GPFINV_BITS
{ // bits description
    Uint32 rsvd1 : 32;
};

union GPFINV_REG
{
    Uint32 all;
    struct GPFINV_BITS bit;
};

struct GPFODR_BITS
{ // bits description
    Uint32 rsvd1 : 32;
};

union GPFODR_REG
{
    Uint32 all;
    struct GPFODR_BITS bit;
};

struct GPFGMUX1_BITS
{ // bits description
    Uint32 rsvd1 : 32;
};

union GPFGMUX1_REG
{
    Uint32 all;
    struct GPFGMUX1_BITS bit;
};

struct GPFGMUX2_BITS
{ // bits description
    Uint32 rsvd1 : 32;
};

union GPFGMUX2_REG
{
    Uint32 all;
    struct GPFGMUX2_BITS bit;
};

struct GPFCSEL1_BITS
{ // bits description
    Uint32 rsvd1 : 32;
};

union GPFCSEL1_REG
{
    Uint32 all;
    struct GPFCSEL1_BITS bit;
};

struct GPFCSEL2_BITS
{ // bits description
    Uint32 rsvd1 : 32;
};

union GPFCSEL2_REG
{
    Uint32 all;
    struct GPFCSEL2_BITS bit;
};

struct GPFCSEL3_BITS
{ // bits description
    Uint32 rsvd1 : 32;
};

union GPFCSEL3_REG
{
    Uint32 all;
    struct GPFCSEL3_BITS bit;
};

struct GPFCSEL4_BITS
{ // bits description
    Uint32 rsvd1 : 32;
};

union GPFCSEL4_REG
{
    Uint32 all;
    struct GPFCSEL4_BITS bit;
};

struct GPFLOCK_BITS
{ // bits description
    Uint32 rsvd1 : 32;
};

union GPFLOCK_REG
{
    Uint32 all;
    struct GPFLOCK_BITS bit;
};

struct GPFCR_BITS
{ // bits description
    Uint32 rsvd1 : 32;
};

union GPFCR_REG
{
    Uint32 all;
    struct GPFCR_BITS bit;
};

struct GPGCTRL_BITS
{                        // bits description
    Uint32 QUALPRD0 : 8; // 7:0 Qualification sampling period for GPIO198 to GPIO199
    Uint32 QUALPRD1 : 8; // 15:8 Qualification sampling period for GPIO200 to GPIO207
    Uint32 QUALPRD2 : 8; // 23:16 Qualification sampling period for GPIO208 to GPIO215
    Uint32 QUALPRD3 : 8; // 31:14 Qualification sampling period for GPIO216 to GPIO223
};

union GPGCTRL_REG
{
    Uint32 all;
    struct GPGCTRL_BITS bit;
};

struct GPGQSEL1_BITS
{                       // bits description
    Uint32 rsvd1   : 2; // 1:0 Reserved
    Uint32 rsvd2   : 2; // 3:2 Reserved
    Uint32 rsvd3   : 2; // 5:4 Reserved
    Uint32 rsvd4   : 2; // 7:6 Reserved
    Uint32 rsvd5   : 2; // 9:8 Reserved
    Uint32 rsvd6   : 2; // 11:10 Reserved
    Uint32 GPIO198 : 2; // 13:12 Select input qualification type for GPIO198
    Uint32 GPIO199 : 2; // 15:14 Select input qualification type for GPIO199
    Uint32 GPIO200 : 2; // 17:16 Select input qualification type for GPIO200
    Uint32 GPIO201 : 2; // 19:18 Select input qualification type for GPIO201
    Uint32 GPIO202 : 2; // 21:20 Select input qualification type for GPIO202
    Uint32 GPIO203 : 2; // 23:22 Select input qualification type for GPIO203
    Uint32 GPIO204 : 2; // 25:24 Select input qualification type for GPIO204
    Uint32 GPIO205 : 2; // 27:26 Select input qualification type for GPIO205
    Uint32 GPIO206 : 2; // 29:28 Select input qualification type for GPIO206
    Uint32 GPIO207 : 2; // 31:30 Select input qualification type for GPIO207
};

union GPGQSEL1_REG
{
    Uint32 all;
    struct GPGQSEL1_BITS bit;
};

struct GPGQSEL2_BITS
{                       // bits description
    Uint32 GPIO208 : 2; // 1:0 Select input qualification type for GPIO208
    Uint32 GPIO209 : 2; // 3:2 Select input qualification type for GPIO209
    Uint32 GPIO210 : 2; // 5:4 Select input qualification type for GPIO210
    Uint32 GPIO211 : 2; // 7:6 Select input qualification type for GPIO211
    Uint32 GPIO212 : 2; // 9:8 Select input qualification type for GPIO212
    Uint32 GPIO213 : 2; // 11:10 Select input qualification type for GPIO213
    Uint32 GPIO214 : 2; // 13:12 Select input qualification type for GPIO214
    Uint32 GPIO215 : 2; // 15:14 Select input qualification type for GPIO215
    Uint32 GPIO216 : 2; // 17:16 Select input qualification type for GPIO216
    Uint32 GPIO217 : 2; // 19:18 Select input qualification type for GPIO217
    Uint32 GPIO218 : 2; // 21:20 Select input qualification type for GPIO218
    Uint32 GPIO219 : 2; // 23:22 Select input qualification type for GPIO219
    Uint32 GPIO220 : 2; // 25:24 Select input qualification type for GPIO220
    Uint32 GPIO221 : 2; // 27:26 Select input qualification type for GPIO221
    Uint32 GPIO222 : 2; // 29:28 Select input qualification type for GPIO222
    Uint32 GPIO223 : 2; // 31:30 Select input qualification type for GPIO223
};

union GPGQSEL2_REG
{
    Uint32 all;
    struct GPGQSEL2_BITS bit;
};

struct GPGMUX1_BITS
{                       // bits description
    Uint32 rsvd1   : 2; // 1:0 Reserved
    Uint32 rsvd2   : 2; // 3:2 Reserved
    Uint32 rsvd3   : 2; // 5:4 Reserved
    Uint32 rsvd4   : 2; // 7:6 Reserved
    Uint32 rsvd5   : 2; // 9:8 Reserved
    Uint32 rsvd6   : 2; // 11:10 Reserved
    Uint32 GPIO198 : 2; // 13:12 Defines pin-muxing selection for GPIO198
    Uint32 GPIO199 : 2; // 15:14 Defines pin-muxing selection for GPIO199
    Uint32 GPIO200 : 2; // 17:16 Defines pin-muxing selection for GPIO200
    Uint32 GPIO201 : 2; // 19:18 Defines pin-muxing selection for GPIO201
    Uint32 GPIO202 : 2; // 21:20 Defines pin-muxing selection for GPIO202
    Uint32 GPIO203 : 2; // 23:22 Defines pin-muxing selection for GPIO203
    Uint32 GPIO204 : 2; // 25:24 Defines pin-muxing selection for GPIO204
    Uint32 GPIO205 : 2; // 27:26 Defines pin-muxing selection for GPIO205
    Uint32 GPIO206 : 2; // 29:28 Defines pin-muxing selection for GPIO206
    Uint32 GPIO207 : 2; // 31:30 Defines pin-muxing selection for GPIO207
};

union GPGMUX1_REG
{
    Uint32 all;
    struct GPGMUX1_BITS bit;
};

struct GPGMUX2_BITS
{                       // bits description
    Uint32 GPIO208 : 2; // 1:0 Defines pin-muxing selection for GPIO208
    Uint32 GPIO209 : 2; // 3:2 Defines pin-muxing selection for GPIO209
    Uint32 GPIO210 : 2; // 5:4 Defines pin-muxing selection for GPIO210
    Uint32 GPIO211 : 2; // 7:6 Defines pin-muxing selection for GPIO211
    Uint32 GPIO212 : 2; // 9:8 Defines pin-muxing selection for GPIO212
    Uint32 GPIO213 : 2; // 11:10 Defines pin-muxing selection for GPIO213
    Uint32 GPIO214 : 2; // 13:12 Defines pin-muxing selection for GPIO214
    Uint32 GPIO215 : 2; // 15:14 Defines pin-muxing selection for GPIO215
    Uint32 GPIO216 : 2; // 17:16 Defines pin-muxing selection for GPIO216
    Uint32 GPIO217 : 2; // 19:18 Defines pin-muxing selection for GPIO217
    Uint32 GPIO218 : 2; // 21:20 Defines pin-muxing selection for GPIO218
    Uint32 GPIO219 : 2; // 23:22 Defines pin-muxing selection for GPIO219
    Uint32 GPIO220 : 2; // 25:24 Defines pin-muxing selection for GPIO220
    Uint32 GPIO221 : 2; // 27:26 Defines pin-muxing selection for GPIO221
    Uint32 GPIO222 : 2; // 29:28 Defines pin-muxing selection for GPIO222
    Uint32 GPIO223 : 2; // 31:30 Defines pin-muxing selection for GPIO223
};

union GPGMUX2_REG
{
    Uint32 all;
    struct GPGMUX2_BITS bit;
};

struct GPGDIR_BITS
{                       // bits description
    Uint32 rsvd1   : 1; // 0 Reserved
    Uint32 rsvd2   : 1; // 1 Reserved
    Uint32 rsvd3   : 1; // 2 Reserved
    Uint32 rsvd4   : 1; // 3 Reserved
    Uint32 rsvd5   : 1; // 4 Reserved
    Uint32 rsvd6   : 1; // 5 Reserved
    Uint32 GPIO198 : 1; // 6 Defines direction for this pin in GPIO mode
    Uint32 GPIO199 : 1; // 7 Defines direction for this pin in GPIO mode
    Uint32 GPIO200 : 1; // 8 Defines direction for this pin in GPIO mode
    Uint32 GPIO201 : 1; // 9 Defines direction for this pin in GPIO mode
    Uint32 GPIO202 : 1; // 10 Defines direction for this pin in GPIO mode
    Uint32 GPIO203 : 1; // 11 Defines direction for this pin in GPIO mode
    Uint32 GPIO204 : 1; // 12 Defines direction for this pin in GPIO mode
    Uint32 GPIO205 : 1; // 13 Defines direction for this pin in GPIO mode
    Uint32 GPIO206 : 1; // 14 Defines direction for this pin in GPIO mode
    Uint32 GPIO207 : 1; // 15 Defines direction for this pin in GPIO mode
    Uint32 GPIO208 : 1; // 16 Defines direction for this pin in GPIO mode
    Uint32 GPIO209 : 1; // 17 Defines direction for this pin in GPIO mode
    Uint32 GPIO210 : 1; // 18 Defines direction for this pin in GPIO mode
    Uint32 GPIO211 : 1; // 19 Defines direction for this pin in GPIO mode
    Uint32 GPIO212 : 1; // 20 Defines direction for this pin in GPIO mode
    Uint32 GPIO213 : 1; // 21 Defines direction for this pin in GPIO mode
    Uint32 GPIO214 : 1; // 22 Defines direction for this pin in GPIO mode
    Uint32 GPIO215 : 1; // 23 Defines direction for this pin in GPIO mode
    Uint32 GPIO216 : 1; // 24 Defines direction for this pin in GPIO mode
    Uint32 GPIO217 : 1; // 25 Defines direction for this pin in GPIO mode
    Uint32 GPIO218 : 1; // 26 Defines direction for this pin in GPIO mode
    Uint32 GPIO219 : 1; // 27 Defines direction for this pin in GPIO mode
    Uint32 GPIO220 : 1; // 28 Defines direction for this pin in GPIO mode
    Uint32 GPIO221 : 1; // 29 Defines direction for this pin in GPIO mode
    Uint32 GPIO222 : 1; // 30 Defines direction for this pin in GPIO mode
    Uint32 GPIO223 : 1; // 31 Defines direction for this pin in GPIO mode
};

union GPGDIR_REG
{
    Uint32 all;
    struct GPGDIR_BITS bit;
};

struct GPGPUD_BITS
{                       // bits description
    Uint32 rsvd1   : 1; // 0 Reserved
    Uint32 rsvd2   : 1; // 1 Reserved
    Uint32 rsvd3   : 1; // 2 Reserved
    Uint32 rsvd4   : 1; // 3 Reserved
    Uint32 rsvd5   : 1; // 4 Reserved
    Uint32 rsvd6   : 1; // 5 Reserved
    Uint32 GPIO198 : 1; // 6 Pull-Up Disable control for this pin
    Uint32 GPIO199 : 1; // 7 Pull-Up Disable control for this pin
    Uint32 GPIO200 : 1; // 8 Pull-Up Disable control for this pin
    Uint32 GPIO201 : 1; // 9 Pull-Up Disable control for this pin
    Uint32 GPIO202 : 1; // 10 Pull-Up Disable control for this pin
    Uint32 GPIO203 : 1; // 11 Pull-Up Disable control for this pin
    Uint32 GPIO204 : 1; // 12 Pull-Up Disable control for this pin
    Uint32 GPIO205 : 1; // 13 Pull-Up Disable control for this pin
    Uint32 GPIO206 : 1; // 14 Pull-Up Disable control for this pin
    Uint32 GPIO207 : 1; // 15 Pull-Up Disable control for this pin
    Uint32 GPIO208 : 1; // 16 Pull-Up Disable control for this pin
    Uint32 GPIO209 : 1; // 17 Pull-Up Disable control for this pin
    Uint32 GPIO210 : 1; // 18 Pull-Up Disable control for this pin
    Uint32 GPIO211 : 1; // 19 Pull-Up Disable control for this pin
    Uint32 GPIO212 : 1; // 20 Pull-Up Disable control for this pin
    Uint32 GPIO213 : 1; // 21 Pull-Up Disable control for this pin
    Uint32 GPIO214 : 1; // 22 Pull-Up Disable control for this pin
    Uint32 GPIO215 : 1; // 23 Pull-Up Disable control for this pin
    Uint32 GPIO216 : 1; // 24 Pull-Up Disable control for this pin
    Uint32 GPIO217 : 1; // 25 Pull-Up Disable control for this pin
    Uint32 GPIO218 : 1; // 26 Pull-Up Disable control for this pin
    Uint32 GPIO219 : 1; // 27 Pull-Up Disable control for this pin
    Uint32 GPIO220 : 1; // 28 Pull-Up Disable control for this pin
    Uint32 GPIO221 : 1; // 29 Pull-Up Disable control for this pin
    Uint32 GPIO222 : 1; // 30 Pull-Up Disable control for this pin
    Uint32 GPIO223 : 1; // 31 Pull-Up Disable control for this pin
};

union GPGPUD_REG
{
    Uint32 all;
    struct GPGPUD_BITS bit;
};

struct GPGINV_BITS
{                       // bits description
    Uint32 rsvd1   : 1; // 0 Reserved
    Uint32 rsvd2   : 1; // 1 Reserved
    Uint32 rsvd3   : 1; // 2 Reserved
    Uint32 rsvd4   : 1; // 3 Reserved
    Uint32 rsvd5   : 1; // 4 Reserved
    Uint32 rsvd6   : 1; // 5 Reserved
    Uint32 GPIO198 : 1; // 6 Input inversion control for this pin
    Uint32 GPIO199 : 1; // 7 Input inversion control for this pin
    Uint32 GPIO200 : 1; // 8 Input inversion control for this pin
    Uint32 GPIO201 : 1; // 9 Input inversion control for this pin
    Uint32 GPIO202 : 1; // 10 Input inversion control for this pin
    Uint32 GPIO203 : 1; // 11 Input inversion control for this pin
    Uint32 GPIO204 : 1; // 12 Input inversion control for this pin
    Uint32 GPIO205 : 1; // 13 Input inversion control for this pin
    Uint32 GPIO206 : 1; // 14 Input inversion control for this pin
    Uint32 GPIO207 : 1; // 15 Input inversion control for this pin
    Uint32 GPIO208 : 1; // 16 Input inversion control for this pin
    Uint32 GPIO209 : 1; // 17 Input inversion control for this pin
    Uint32 GPIO210 : 1; // 18 Input inversion control for this pin
    Uint32 GPIO211 : 1; // 19 Input inversion control for this pin
    Uint32 GPIO212 : 1; // 20 Input inversion control for this pin
    Uint32 GPIO213 : 1; // 21 Input inversion control for this pin
    Uint32 GPIO214 : 1; // 22 Input inversion control for this pin
    Uint32 GPIO215 : 1; // 23 Input inversion control for this pin
    Uint32 GPIO216 : 1; // 24 Input inversion control for this pin
    Uint32 GPIO217 : 1; // 25 Input inversion control for this pin
    Uint32 GPIO218 : 1; // 26 Input inversion control for this pin
    Uint32 GPIO219 : 1; // 27 Input inversion control for this pin
    Uint32 GPIO220 : 1; // 28 Input inversion control for this pin
    Uint32 GPIO221 : 1; // 29 Input inversion control for this pin
    Uint32 GPIO222 : 1; // 30 Input inversion control for this pin
    Uint32 GPIO223 : 1; // 31 Input inversion control for this pin
};

union GPGINV_REG
{
    Uint32 all;
    struct GPGINV_BITS bit;
};

struct GPGODR_BITS
{                       // bits description
    Uint32 rsvd1   : 1; // 0 Reserved
    Uint32 rsvd2   : 1; // 1 Reserved
    Uint32 rsvd3   : 1; // 2 Reserved
    Uint32 rsvd4   : 1; // 3 Reserved
    Uint32 rsvd5   : 1; // 4 Reserved
    Uint32 rsvd6   : 1; // 5 Reserved
    Uint32 GPIO198 : 1; // 6 Output Open-Drain control for this pin
    Uint32 GPIO199 : 1; // 7 Output Open-Drain control for this pin
    Uint32 GPIO200 : 1; // 8 Output Open-Drain control for this pin
    Uint32 GPIO201 : 1; // 9 Output Open-Drain control for this pin
    Uint32 GPIO202 : 1; // 10 Output Open-Drain control for this pin
    Uint32 GPIO203 : 1; // 11 Output Open-Drain control for this pin
    Uint32 GPIO204 : 1; // 12 Output Open-Drain control for this pin
    Uint32 GPIO205 : 1; // 13 Output Open-Drain control for this pin
    Uint32 GPIO206 : 1; // 14 Output Open-Drain control for this pin
    Uint32 GPIO207 : 1; // 15 Output Open-Drain control for this pin
    Uint32 GPIO208 : 1; // 16 Output Open-Drain control for this pin
    Uint32 GPIO209 : 1; // 17 Output Open-Drain control for this pin
    Uint32 GPIO210 : 1; // 18 Output Open-Drain control for this pin
    Uint32 GPIO211 : 1; // 19 Output Open-Drain control for this pin
    Uint32 GPIO212 : 1; // 20 Output Open-Drain control for this pin
    Uint32 GPIO213 : 1; // 21 Output Open-Drain control for this pin
    Uint32 GPIO214 : 1; // 22 Output Open-Drain control for this pin
    Uint32 GPIO215 : 1; // 23 Output Open-Drain control for this pin
    Uint32 GPIO216 : 1; // 24 Output Open-Drain control for this pin
    Uint32 GPIO217 : 1; // 25 Output Open-Drain control for this pin
    Uint32 GPIO218 : 1; // 26 Output Open-Drain control for this pin
    Uint32 GPIO219 : 1; // 27 Output Open-Drain control for this pin
    Uint32 GPIO220 : 1; // 28 Output Open-Drain control for this pin
    Uint32 GPIO221 : 1; // 29 Output Open-Drain control for this pin
    Uint32 GPIO222 : 1; // 30 Output Open-Drain control for this pin
    Uint32 GPIO223 : 1; // 31 Output Open-Drain control for this pin
};

union GPGODR_REG
{
    Uint32 all;
    struct GPGODR_BITS bit;
};

struct GPGAMSEL_BITS
{                       // bits description
    Uint32 rsvd1   : 1; // 0 Reserved
    Uint32 rsvd2   : 1; // 1 Reserved
    Uint32 rsvd3   : 1; // 2 Reserved
    Uint32 rsvd4   : 1; // 3 Reserved
    Uint32 rsvd5   : 1; // 4 Reserved
    Uint32 rsvd6   : 1; // 5 Reserved
    Uint32 GPIO198 : 1; // 6 Analog Mode select for this pin
    Uint32 GPIO199 : 1; // 7 Analog Mode select for this pin
    Uint32 GPIO200 : 1; // 8 Analog Mode select for this pin
    Uint32 GPIO201 : 1; // 9 Analog Mode select for this pin
    Uint32 GPIO202 : 1; // 10 Analog Mode select for this pin
    Uint32 GPIO203 : 1; // 11 Analog Mode select for this pin
    Uint32 GPIO204 : 1; // 12 Analog Mode select for this pin
    Uint32 GPIO205 : 1; // 13 Analog Mode select for this pin
    Uint32 GPIO206 : 1; // 14 Analog Mode select for this pin
    Uint32 GPIO207 : 1; // 15 Analog Mode select for this pin
    Uint32 GPIO208 : 1; // 16 Analog Mode select for this pin
    Uint32 GPIO209 : 1; // 17 Analog Mode select for this pin
    Uint32 GPIO210 : 1; // 18 Analog Mode select for this pin
    Uint32 GPIO211 : 1; // 19 Analog Mode select for this pin
    Uint32 GPIO212 : 1; // 20 Analog Mode select for this pin
    Uint32 GPIO213 : 1; // 21 Analog Mode select for this pin
    Uint32 GPIO214 : 1; // 22 Analog Mode select for this pin
    Uint32 GPIO215 : 1; // 23 Analog Mode select for this pin
    Uint32 GPIO216 : 1; // 24 Analog Mode select for this pin
    Uint32 GPIO217 : 1; // 25 Analog Mode select for this pin
    Uint32 GPIO218 : 1; // 26 Analog Mode select for this pin
    Uint32 GPIO219 : 1; // 27 Analog Mode select for this pin
    Uint32 rdvd7   : 4; // 31:28 Reserved
};

union GPGAMSEL_REG
{
    Uint32 all;
    struct GPGAMSEL_BITS bit;
};

struct GPGGMUX1_BITS
{                       // bits description
    Uint32 rsvd1   : 2; // 1:0 Reserved
    Uint32 rsvd2   : 2; // 3:2 Reserved
    Uint32 rsvd3   : 2; // 5:4 Reserved
    Uint32 rsvd4   : 2; // 7:6 Reserved
    Uint32 rsvd5   : 2; // 9:8 Reserved
    Uint32 rsvd6   : 2; // 11:10 Reserved
    Uint32 GPIO198 : 2; // 13:12 Defines pin-muxing selection for GPIO198
    Uint32 GPIO199 : 2; // 15:14 Defines pin-muxing selection for GPIO199
    Uint32 GPIO200 : 2; // 17:16 Defines pin-muxing selection for GPIO200
    Uint32 GPIO201 : 2; // 19:18 Defines pin-muxing selection for GPIO201
    Uint32 GPIO202 : 2; // 21:20 Defines pin-muxing selection for GPIO202
    Uint32 GPIO203 : 2; // 23:22 Defines pin-muxing selection for GPIO203
    Uint32 GPIO204 : 2; // 25:24 Defines pin-muxing selection for GPIO204
    Uint32 GPIO205 : 2; // 27:26 Defines pin-muxing selection for GPIO205
    Uint32 GPIO206 : 2; // 29:28 Defines pin-muxing selection for GPIO206
    Uint32 GPIO207 : 2; // 31:30 Defines pin-muxing selection for GPIO207
};

union GPGGMUX1_REG
{
    Uint32 all;
    struct GPGGMUX1_BITS bit;
};

struct GPGGMUX2_BITS
{                       // bits description
    Uint32 GPIO208 : 2; // 1:0 Defines pin-muxing selection for GPIO208
    Uint32 GPIO209 : 2; // 3:2 Defines pin-muxing selection for GPIO209
    Uint32 GPIO210 : 2; // 5:4 Defines pin-muxing selection for GPIO210
    Uint32 GPIO211 : 2; // 7:6 Defines pin-muxing selection for GPIO211
    Uint32 GPIO212 : 2; // 9:8 Defines pin-muxing selection for GPIO212
    Uint32 GPIO213 : 2; // 11:10 Defines pin-muxing selection for GPIO213
    Uint32 GPIO214 : 2; // 13:12 Defines pin-muxing selection for GPIO214
    Uint32 GPIO215 : 2; // 15:14 Defines pin-muxing selection for GPIO215
    Uint32 GPIO216 : 2; // 17:16 Defines pin-muxing selection for GPIO216
    Uint32 GPIO217 : 2; // 19:18 Defines pin-muxing selection for GPIO217
    Uint32 GPIO218 : 2; // 21:20 Defines pin-muxing selection for GPIO218
    Uint32 GPIO219 : 2; // 23:22 Defines pin-muxing selection for GPIO219
    Uint32 GPIO220 : 2; // 25:24 Defines pin-muxing selection for GPIO220
    Uint32 GPIO221 : 2; // 27:26 Defines pin-muxing selection for GPIO221
    Uint32 GPIO222 : 2; // 29:28 Defines pin-muxing selection for GPIO222
    Uint32 GPIO223 : 2; // 31:30 Defines pin-muxing selection for GPIO223
};

union GPGGMUX2_REG
{
    Uint32 all;
    struct GPGGMUX2_BITS bit;
};

struct GPGCSEL1_BITS
{                       // bits description
    Uint32 rsvd1   : 4; // 3:0 Reserved
    Uint32 rsvd2   : 4; // 7:4 Reserved
    Uint32 rsvd3   : 4; // 11:8 Reserved
    Uint32 rsvd4   : 4; // 15:12 Reserved
    Uint32 rsvd5   : 4; // 19:16 Reserved
    Uint32 rsvd6   : 4; // 23:20 Reserved
    Uint32 GPIO198 : 4; // 27:24 GPIO198 Controller CPU Select
    Uint32 GPIO199 : 4; // 31:28 GPIO199 Controller CPU Select
};

union GPGCSEL1_REG
{
    Uint32 all;
    struct GPGCSEL1_BITS bit;
};

struct GPGCSEL2_BITS
{                       // bits description
    Uint32 GPIO200 : 4; // 3:0 GPIO200 Controller CPU Select
    Uint32 GPIO201 : 4; // 7:4 GPIO201 Controller CPU Select
    Uint32 GPIO202 : 4; // 11:8 GPIO202 Controller CPU Select
    Uint32 GPIO203 : 4; // 15:12 GPIO203 Controller CPU Select
    Uint32 GPIO204 : 4; // 19:16 GPIO204 Controller CPU Select
    Uint32 GPIO205 : 4; // 23:20 GPIO205 Controller CPU Select
    Uint32 GPIO206 : 4; // 27:24 GPIO206 Controller CPU Select
    Uint32 GPIO207 : 4; // 31:28 GPIO207 Controller CPU Select
};

union GPGCSEL2_REG
{
    Uint32 all;
    struct GPGCSEL2_BITS bit;
};

struct GPGCSEL3_BITS
{                       // bits description
    Uint32 GPIO208 : 4; // 3:0 GPIO208 Controller CPU Select
    Uint32 GPIO209 : 4; // 7:4 GPIO209 Controller CPU Select
    Uint32 GPIO210 : 4; // 11:8 GPIO210 Controller CPU Select
    Uint32 GPIO211 : 4; // 15:12 GPIO211 Controller CPU Select
    Uint32 GPIO212 : 4; // 19:16 GPIO212 Controller CPU Select
    Uint32 GPIO213 : 4; // 23:20 GPIO213 Controller CPU Select
    Uint32 GPIO214 : 4; // 27:24 GPIO214 Controller CPU Select
    Uint32 GPIO215 : 4; // 31:28 GPIO215 Controller CPU Select
};

union GPGCSEL3_REG
{
    Uint32 all;
    struct GPGCSEL3_BITS bit;
};

struct GPGCSEL4_BITS
{                       // bits description
    Uint32 GPIO216 : 4; // 3:0 GPIO216 Controller CPU Select
    Uint32 GPIO217 : 4; // 7:4 GPIO217 Controller CPU Select
    Uint32 GPIO218 : 4; // 11:8 GPIO218 Controller CPU Select
    Uint32 GPIO219 : 4; // 15:12 GPIO219 Controller CPU Select
    Uint32 GPIO220 : 4; // 19:16 GPIO220 Controller CPU Select
    Uint32 GPIO221 : 4; // 23:20 GPIO221 Controller CPU Select
    Uint32 GPIO222 : 4; // 27:24 GPIO222 Controller CPU Select
    Uint32 GPIO223 : 4; // 31:28 GPIO223 Controller CPU Select
};

union GPGCSEL4_REG
{
    Uint32 all;
    struct GPGCSEL4_BITS bit;
};

struct GPGLOCK_BITS
{                       // bits description
    Uint32 rsvd1   : 1; // 0 Reserved
    Uint32 rsvd2   : 1; // 1 Reserved
    Uint32 rsvd3   : 1; // 2 Reserved
    Uint32 rsvd4   : 1; // 3 Reserved
    Uint32 rsvd5   : 1; // 4 Reserved
    Uint32 rsvd6   : 1; // 5 Reserved
    Uint32 GPIO198 : 1; // 6 Configuration Lock bit for this pin
    Uint32 GPIO199 : 1; // 7 Configuration Lock bit for this pin
    Uint32 GPIO200 : 1; // 8 Configuration Lock bit for this pin
    Uint32 GPIO201 : 1; // 9 Configuration Lock bit for this pin
    Uint32 GPIO202 : 1; // 10 Configuration Lock bit for this pin
    Uint32 GPIO203 : 1; // 11 Configuration Lock bit for this pin
    Uint32 GPIO204 : 1; // 12 Configuration Lock bit for this pin
    Uint32 GPIO205 : 1; // 13 Configuration Lock bit for this pin
    Uint32 GPIO206 : 1; // 14 Configuration Lock bit for this pin
    Uint32 GPIO207 : 1; // 15 Configuration Lock bit for this pin
    Uint32 GPIO208 : 1; // 16 Configuration Lock bit for this pin
    Uint32 GPIO209 : 1; // 17 Configuration Lock bit for this pin
    Uint32 GPIO210 : 1; // 18 Configuration Lock bit for this pin
    Uint32 GPIO211 : 1; // 19 Configuration Lock bit for this pin
    Uint32 GPIO212 : 1; // 20 Configuration Lock bit for this pin
    Uint32 GPIO213 : 1; // 21 Configuration Lock bit for this pin
    Uint32 GPIO214 : 1; // 22 Configuration Lock bit for this pin
    Uint32 GPIO215 : 1; // 23 Configuration Lock bit for this pin
    Uint32 GPIO216 : 1; // 24 Configuration Lock bit for this pin
    Uint32 GPIO217 : 1; // 25 Configuration Lock bit for this pin
    Uint32 GPIO218 : 1; // 26 Configuration Lock bit for this pin
    Uint32 GPIO219 : 1; // 27 Configuration Lock bit for this pin
    Uint32 GPIO220 : 1; // 28 Configuration Lock bit for this pin
    Uint32 GPIO221 : 1; // 29 Configuration Lock bit for this pin
    Uint32 GPIO222 : 1; // 30 Configuration Lock bit for this pin
    Uint32 GPIO223 : 1; // 31 Configuration Lock bit for this pin
};

union GPGLOCK_REG
{
    Uint32 all;
    struct GPGLOCK_BITS bit;
};

struct GPGCR_BITS
{                       // bits description
    Uint32 rsvd1   : 1; // 0 Reserved
    Uint32 rsvd2   : 1; // 1 Reserved
    Uint32 rsvd3   : 1; // 2 Reserved
    Uint32 rsvd4   : 1; // 3 Reserved
    Uint32 rsvd5   : 1; // 4 Reserved
    Uint32 rsvd6   : 1; // 5 Reserved
    Uint32 GPIO198 : 1; // 6 Configuration lock commit bit for this pin
    Uint32 GPIO199 : 1; // 7 Configuration lock commit bit for this pin
    Uint32 GPIO200 : 1; // 8 Configuration lock commit bit for this pin
    Uint32 GPIO201 : 1; // 9 Configuration lock commit bit for this pin
    Uint32 GPIO202 : 1; // 10 Configuration lock commit bit for this pin
    Uint32 GPIO203 : 1; // 11 Configuration lock commit bit for this pin
    Uint32 GPIO204 : 1; // 12 Configuration lock commit bit for this pin
    Uint32 GPIO205 : 1; // 13 Configuration lock commit bit for this pin
    Uint32 GPIO206 : 1; // 14 Configuration lock commit bit for this pin
    Uint32 GPIO207 : 1; // 15 Configuration lock commit bit for this pin
    Uint32 GPIO208 : 1; // 16 Configuration lock commit bit for this pin
    Uint32 GPIO209 : 1; // 17 Configuration lock commit bit for this pin
    Uint32 GPIO210 : 1; // 18 Configuration lock commit bit for this pin
    Uint32 GPIO211 : 1; // 19 Configuration lock commit bit for this pin
    Uint32 GPIO212 : 1; // 20 Configuration lock commit bit for this pin
    Uint32 GPIO213 : 1; // 21 Configuration lock commit bit for this pin
    Uint32 GPIO214 : 1; // 22 Configuration lock commit bit for this pin
    Uint32 GPIO215 : 1; // 23 Configuration lock commit bit for this pin
    Uint32 GPIO216 : 1; // 24 Configuration lock commit bit for this pin
    Uint32 GPIO217 : 1; // 25 Configuration lock commit bit for this pin
    Uint32 GPIO218 : 1; // 26 Configuration lock commit bit for this pin
    Uint32 GPIO219 : 1; // 27 Configuration lock commit bit for this pin
    Uint32 GPIO220 : 1; // 28 Configuration lock commit bit for this pin
    Uint32 GPIO221 : 1; // 29 Configuration lock commit bit for this pin
    Uint32 GPIO222 : 1; // 30 Configuration lock commit bit for this pin
    Uint32 GPIO223 : 1; // 31 Configuration lock commit bit for this pin
};

union GPGCR_REG
{
    Uint32 all;
    struct GPGCR_BITS bit;
};

struct GPHCTRL_BITS
{                        // bits description
    Uint32 QUALPRD0 : 8; // 7:0 Qualification sampling period for GPIO224 to GPIO231
};

union GPHCTRL_REG
{
    Uint32 all;
    struct GPHCTRL_BITS bit;
};

struct GPHQSEL1_BITS
{                       // bits description
    Uint32 GPIO224 : 2; // 1:0 Select input qualification type for this GPIO Pin
};

union GPHQSEL1_REG
{
    Uint32 all;
    struct GPHQSEL1_BITS bit;
};

struct GPHQSEL2_BITS
{ // bits description
    Uint32 rsvd1 : 32;
};

union GPHQSEL2_REG
{
    Uint32 all;
    struct GPHQSEL2_BITS bit;
};

struct GPHMUX1_BITS
{                       // bits description
    Uint32 GPIO224 : 2; // 1:0 Defines pin-muxing selection for GPIO224
};

union GPHMUX1_REG
{
    Uint32 all;
    struct GPHMUX1_BITS bit;
};

struct GPHMUX2_BITS
{ // bits description
    Uint32 rsvd1 : 32;
};

union GPHMUX2_REG
{
    Uint32 all;
    struct GPHMUX2_BITS bit;
};

struct GPHDIR_BITS
{                       // bits description
    Uint32 GPIO224 : 1; // 0 Defines direction for this pin in GPIO mode
};

union GPHDIR_REG
{
    Uint32 all;
    struct GPHDIR_BITS bit;
};

struct GPHPUD_BITS
{                       // bits description
    Uint32 GPIO224 : 1; // 0 Pull-Up Disable control for this pin
};

union GPHPUD_REG
{
    Uint32 all;
    struct GPHPUD_BITS bit;
};

struct GPHINV_BITS
{                       // bits description
    Uint32 GPIO224 : 1; // 0 Input inversion control for this pin
};

union GPHINV_REG
{
    Uint32 all;
    struct GPHINV_BITS bit;
};

struct GPHODR_BITS
{                       // bits description
    Uint32 GPIO224 : 1; // 0 Output Open-Drain control for this pin
};

union GPHODR_REG
{
    Uint32 all;
    struct GPHODR_BITS bit;
};

struct GPHAMSEL_BITS
{                       // bits description
    Uint32 rsvd1   : 1; // 0 Reserved
    Uint32 GPIO225 : 1; // 1 Analog Mode select for this pin
    Uint32 GPIO226 : 1; // 2 Analog Mode select for this pin
    Uint32 GPIO227 : 1; // 3 Analog Mode select for this pin
    Uint32 GPIO228 : 1; // 4 Analog Mode select for this pin
    Uint32 GPIO229 : 1; // 5 Analog Mode select for this pin
    Uint32 GPIO230 : 1; // 6 Analog Mode select for this pin
    Uint32 GPIO231 : 1; // 7 Analog Mode select for this pin
    Uint32 GPIO232 : 1; // 8 Analog Mode select for this pin
    Uint32 GPIO233 : 1; // 9 Analog Mode select for this pin
    Uint32 GPIO234 : 1; // 10 Analog Mode select for this pin
    Uint32 GPIO235 : 1; // 11 Analog Mode select for this pin
    Uint32 GPIO236 : 1; // 12 Analog Mode select for this pin
    Uint32 GPIO237 : 1; // 13 Analog Mode select for this pin
    Uint32 rsvd2   : 2; // 15:14 Reserved
    Uint32 GPIO240 : 1; // 16 Analog Mode select for this pin
};

union GPHAMSEL_REG
{
    Uint32 all;
    struct GPHAMSEL_BITS bit;
};

struct GPHGMUX1_BITS
{                       // bits description
    Uint32 GPIO224 : 2; // 1:0 Defines pin-muxing selection for GPIO224
};

union GPHGMUX1_REG
{
    Uint32 all;
    struct GPHGMUX1_BITS bit;
};

struct GPHGMUX2_BITS
{ // bits description
    Uint32 rsvd1 : 32;
};

union GPHGMUX2_REG
{
    Uint32 all;
    struct GPHGMUX2_BITS bit;
};

struct GPHCSEL1_BITS
{                       // bits description
    Uint32 GPIO224 : 4; // 3:0 GPIO224 Controller CPU Select
};

union GPHCSEL1_REG
{
    Uint32 all;
    struct GPHCSEL1_BITS bit;
};

struct GPHCSEL2_BITS
{ // bits description
    Uint32 rsvd1 : 32;
};

union GPHCSEL2_REG
{
    Uint32 all;
    struct GPHCSEL2_BITS bit;
};

struct GPHCSEL3_BITS
{ // bits description
    Uint32 rsvd1 : 32;
};

union GPHCSEL3_REG
{
    Uint32 all;
    struct GPHCSEL3_BITS bit;
};

struct GPHLOCK_BITS
{                       // bits description
    Uint32 GPIO224 : 1; // 0 Configuration Lock bit for this pin
};

union GPHLOCK_REG
{
    Uint32 all;
    struct GPHLOCK_BITS bit;
};

struct GPHCR_BITS
{                       // bits description
    Uint32 GPIO224 : 1; // 0 Configuration lock commit bit for this pin
};

union GPHCR_REG
{
    Uint32 all;
    struct GPHCR_BITS bit;
};

struct GPIO_CTRL_REGS
{
    /* clang-format off */
    union GPACTRL_REG GPACTRL;   // GPIO A Qualification Sampling Period Control (GPIO0 to 31), 0x00
    union GPAQSEL1_REG GPAQSEL1; // GPIO A Qualifier Select 1 Register (GPIO0 to 15), 0x04
    union GPAQSEL2_REG GPAQSEL2; // GPIO A Qualifier Select 2 Register (GPIO16 to 31), 0x08
    union GPAMUX1_REG GPAMUX1;   // GPIO A Mux 1 Register (GPIO0 to 15), 0x0C
    union GPAMUX2_REG GPAMUX2;   // GPIO A Mux 2 Register (GPIO16 to 31), 0x10
    union GPADIR_REG GPADIR;     // GPIO A Direction Register (GPIO0 to 31), 0x14
    union GPAPUD_REG GPAPUD;     // GPIO A Pull Up Disable Register (GPIO0 to 31), 0x18
    union GPAINV_REG GPAINV;     // GPIO A Input Polarity Invert Registers (GPIO0 to 31), 0x1C
    union GPAODR_REG GPAODR;     // GPIO A Open Drain Output Register (GPIO0 to GPIO31), 0x20
    Uint32 rsvd0;                // Reserved, GPAAMSEL, 0x24
    union GPAGMUX1_REG GPAGMUX1; // GPIO A Peripheral Group Mux (GPIO0 to 15), 0x28
    union GPAGMUX2_REG GPAGMUX2; // GPIO A Peripheral Group Mux (GPIO16 to 31), 0x2C
    union GPACSEL1_REG GPACSEL1; // GPIO A Core Select Register (GPIO0 to 7), 0x30
    union GPACSEL2_REG GPACSEL2; // GPIO A Core Select Register (GPIO8 to 15), 0x34
    union GPACSEL3_REG GPACSEL3; // GPIO A Core Select Register (GPIO16 to 23), 0x38
    union GPACSEL4_REG GPACSEL4; // GPIO A Core Select Register (GPIO24 to 31), 0x3C
    union GPALOCK_REG GPALOCK;   // GPIO A Lock Configuration Register (GPIO0 to 31), 0x40
    union GPACR_REG GPACR;       // GPIO A Lock Commit Register (GPIO0 to 31), 0x44
    Uint32 rsvd1[2];             // Reserved, 0x48~0x4C
    union GPBCTRL_REG GPBCTRL;   // GPIO B Qualification Sampling Period Control (GPIO32 to 63), 0x50
    union GPBQSEL1_REG GPBQSEL1; // GPIO B Qualifier Select 1 Register (GPIO32 to 47), 0x54
    union GPBQSEL2_REG GPBQSEL2; // GPIO B Qualifier Select 2 Register (GPIO48 to 63), 0x58
    union GPBMUX1_REG GPBMUX1;   // GPIO B Mux 1 Register (GPIO32 to 47), 0x5C
    union GPBMUX2_REG GPBMUX2;   // GPIO B Mux 2 Register (GPIO48 to 63), 0x60
    union GPBDIR_REG GPBDIR;     // GPIO B Direction Register (GPIO32 to 63), 0x64
    union GPBPUD_REG GPBPUD;     // GPIO B Pull Up Disable Register (GPIO32 to 63), 0x68
    union GPBINV_REG GPBINV;     // GPIO B Input Polarity Invert Registers (GPIO32 to 63), 0x6C
    union GPBODR_REG GPBODR;     // GPIO B Open Drain Output Register (GPIO32 to GPIO63), 0x70
    union GPBAMSEL_REG GPBAMSEL; // GPIO B Analog Mode Select register (GPIO32 to GPIO63), 0x74
    union GPBGMUX1_REG GPBGMUX1; // GPIO B Peripheral Group Mux (GPIO32 to 47), 0x78
    union GPBGMUX2_REG GPBGMUX2; // GPIO B Peripheral Group Mux (GPIO48 to 63), 0x7C
    union GPBCSEL1_REG GPBCSEL1; // GPIO B Core Select Register (GPIO32 to 39), 0x80
    union GPBCSEL2_REG GPBCSEL2; // GPIO B Core Select Register (GPIO40 to 47), 0x84
    union GPBCSEL3_REG GPBCSEL3; // GPIO B Core Select Register (GPIO48 to 55), 0x88
    union GPBCSEL4_REG GPBCSEL4; // GPIO B Core Select Register (GPIO56 to 63), 0x8C
    union GPBLOCK_REG GPBLOCK;   // GPIO B Lock Configuration Register (GPIO32 to 63), 0x90
    union GPBCR_REG GPBCR;       // GPIO B Lock Commit Register (GPIO32 to 63), 0x94
    Uint32 rsvd2[2];             // Reserved, 0x98~0x9C
    union GPCCTRL_REG GPCCTRL; // GPIO C Qualification Sampling Period Control (GPIO64 to 94), 0xA0
    union GPCQSEL1_REG GPCQSEL1; // GPIO C Qualifier Select 1 Register (GPIO64 to 79), 0xA4
    union GPCQSEL2_REG GPCQSEL2; // GPIO C Qualifier Select 2 Register (GPIO80  to 94), 0xA8
    union GPCMUX1_REG GPCMUX1;   // GPIO C Mux 1 Register (GPIO64 to 79), 0xAC
    union GPCMUX2_REG GPCMUX2;   // GPIO C Mux 2 Register (GPIO80  to 94), 0xB0
    union GPCDIR_REG GPCDIR;     // GPIO C Direction Register (GPIO64 to 94), 0xB4
    union GPCPUD_REG GPCPUD;     // GPIO C Pull Up Disable Register (GPIO64 to 94), 0xB8
    union GPCINV_REG GPCINV;     // GPIO C Input Polarity Invert Registers (GPIO64 to 94), 0xBC
    union GPCODR_REG GPCODR;     // GPIO C Open Drain Output Register (GPIO64 to GPIO94), 0xC0
    Uint32 rsvd3;                // Reserved, GPCAMSEL, 0xC4
    union GPCGMUX1_REG GPCGMUX1; // GPIO C Peripheral Group Mux (GPIO64 to 79), 0xC8
    union GPCGMUX2_REG GPCGMUX2; // GPIO C Peripheral Group Mux (GPIO80  to 94), 0xCC
    union GPCCSEL1_REG GPCCSEL1; // GPIO C Core Select Register (GPIO64 to 71), 0xD0
    union GPCCSEL2_REG GPCCSEL2; // GPIO C Core Select Register (GPIO72 to 79), 0xD4
    union GPCCSEL3_REG GPCCSEL3; // GPIO C Core Select Register (GPIO80  to 87), 0xD8
    union GPCCSEL4_REG GPCCSEL4; // GPIO C Core Select Register (GPIO88 to 94), 0xDC
    union GPCLOCK_REG GPCLOCK;   // GPIO C Lock Configuration Register (GPIO64 to 94), 0xE0
    union GPCCR_REG GPCCR;       // GPIO C Lock Commit Register (GPIO64 to 94), 0xE4
    Uint32 rsvd4[2];             // Reserved, 0xE8~0xEC
    union GPDCTRL_REG GPDCTRL; // GPIO D Qualification Sampling Period Control (GPIO99 to 106), 0xF0
    union GPDQSEL1_REG GPDQSEL1; // GPIO D Qualifier Select 1 Register (GPIO99 to 106), 0xF4
    union GPDQSEL2_REG GPDQSEL2; // GPIO D Qualifier Select 2 Register Reserved, 0xF8
    union GPDMUX1_REG GPDMUX1;   // GPIO D Mux 1 Register (GPIO99 to 106), 0xFC
    union GPDMUX2_REG GPDMUX2;   // GPIO D Mux 2 Register Reserved, 0x100
    union GPDDIR_REG GPDDIR;     // GPIO D Direction Register (GPIO99 to 106), 0x104
    union GPDPUD_REG GPDPUD;     // GPIO D Pull Up Disable Register (GPIO99 to 106), 0x108
    union GPDINV_REG GPDINV;     // GPIO D Input Polarity Invert Registers (GPIO99 to 106), 0x10C
    union GPDODR_REG GPDODR;     // GPIO D Open Drain Output Register (GPIO99 to GPIO106), 0x110
    Uint32 rsvd5;                // Reserved, GPDAMSEL, 0x114
    union GPDGMUX1_REG GPDGMUX1; // GPIO D Peripheral Group Mux (GPIO99 to 106), 0x118
    union GPDGMUX2_REG GPDGMUX2; // GPIO D Peripheral Group Mux Reserved, 0x11C
    union GPDCSEL1_REG GPDCSEL1; // GPIO D Core Select Register (GPIO99 to 103), 0x120
    union GPDCSEL2_REG GPDCSEL2; // GPIO D Core Select Register (GPIO104 to 106), 0x124
    union GPDCSEL3_REG GPDCSEL3; // GPIO D Core Select Register Reserved, 0x128
    union GPDCSEL4_REG GPDCSEL4; // GPIO D Core Select Register Reserved, 0x12C
    union GPDLOCK_REG GPDLOCK;   // GPIO D Lock Configuration Register (GPIO99 to 106), 0x130
    union GPDCR_REG GPDCR;       // GPIO D Lock Commit Register (GPIO99 to 106), 0x134
    Uint32 rsvd6[2];             // Reserved, 0x138~0x13C
    union GPECTRL_REG GPECTRL;   // GPIO E Qualification Sampling Period Control (GPIO133), 0x140
    union GPEQSEL1_REG GPEQSEL1; // GPIO E Qualifier Select 1 Register (GPIO133), 0x144
    union GPEQSEL2_REG GPEQSEL2; // GPIO E Qualifier Select 2 Register Reserved, 0x148
    union GPEMUX1_REG GPEMUX1;   // GPIO E Mux 1 Register (GPIO133), 0x14C
    union GPEMUX2_REG GPEMUX2;   // GPIO E Mux 2 Register Reserved, 0x150
    union GPEDIR_REG GPEDIR;     // GPIO E Direction Register (GPIO133), 0x154
    union GPEPUD_REG GPEPUD;     // GPIO E Pull Up Disable Register (GPIO133), 0x158
    union GPEINV_REG GPEINV;     // GPIO E Input Polarity Invert Registers (GPIO133), 0x15C
    union GPEODR_REG GPEODR;     // GPIO E Open Drain Output Register (GPIO133), 0x160
    Uint32 rsvd7;                // Reserved, GPEAMSEL, 0x164
    union GPEGMUX1_REG GPEGMUX1; // GPIO E Peripheral Group Mux (GPIO133), 0x168
    union GPEGMUX2_REG GPEGMUX2; // GPIO E Peripheral Group Mux Reserved, 0x16C
    union GPECSEL1_REG GPECSEL1; // GPIO E Core Select Register (GPIO133), 0x170
    union GPECSEL2_REG GPECSEL2; // GPIO E Core Select Register Reserved, 0x174
    union GPECSEL3_REG GPECSEL3; // GPIO E Core Select Register Reserved, 0x178
    union GPECSEL4_REG GPECSEL4; // GPIO E Core Select Register Reserved, 0x17C
    union GPELOCK_REG GPELOCK;   // GPIO E Lock Configuration Register (GPIO133), 0x180
    union GPECR_REG GPECR;       // GPIO E Lock Commit Register (GPIO133), 0x184
    Uint32 rsvd8[2];             // Reserved, 0x188~0x18C
    union GPFCTRL_REG GPFCTRL;   // GPIO F Qualification Sampling Period Control Reserved, 0x190
    union GPFQSEL1_REG GPFQSEL1; // GPIO F Qualifier Select 1 Register Reserved, 0x194
    union GPFQSEL1_REG GPFQSEL2; // GPIO F Qualifier Select 2 Register Reserved, 0x198
    union GPFMUX1_REG GPFMUX1;   // GPIO F Mux 1 Register Reserved, 0x19C
    union GPFMUX1_REG GPFMUX2;   // GPIO F Mux 2 Register Reserved, 0x1A0
    union GPFDIR_REG GPFDIR;     // GPIO F Direction Register Reserved, 0x1A4
    union GPFPUD_REG GPFPUD;     // GPIO F Pull Up Disable Register Reserved, 0x1A8
    union GPFINV_REG GPFINV;     // GPIO F Input Polarity Invert Registers Reserved, 0x1AC
    union GPFODR_REG GPFODR;     // GPIO F Open Drain Output Register Reserved, 0x1B0
    union GPFODR_REG GPFAMSEL;   // GPIO F Open Drain Output Register Reserved, 0x1B4
    union GPFGMUX1_REG GPFGMUX1; // GPIO F Peripheral Group Mux 1 Reserved, 0x1B8
    union GPFGMUX2_REG GPFGMUX2; // GPIO F Peripheral Group Mux 2 Reserved, 0x1BC
    union GPFCSEL1_REG GPFCSEL1; // GPIO F Core Select Register 1 Reserved, 0x1C0
    union GPFCSEL2_REG GPFCSEL2; // GPIO F Core Select Register 2 Reserved, 0x1C4
    union GPFCSEL3_REG GPFCSEL3; // GPIO F Core Select Register 3 Reserved, 0x1C8
    union GPFCSEL4_REG GPFCSEL4; // GPIO F Core Select Register 4 Reserved, 0x1CC
    union GPFLOCK_REG GPFLOCK;   // GPIO F Lock Configuration Register Reserved, 0x1D0
    union GPFCR_REG GPFCR;       // GPIO F Lock Commit Register Reserved, 0x1D4
    Uint32 rsvd10[2];            // Reserved, 0x1D8~0x1DC
    union GPGCTRL_REG GPGCTRL;   // GPIO G Qualification Sampling Period Control (GPIO198 to 223), 0x1E0
    union GPGQSEL1_REG GPGQSEL1; // GPIO G Qualifier Select 1 Register (GPIO198 to 207), 0x1E4
    union GPGQSEL2_REG GPGQSEL2; // GPIO G Qualifier Select 2 Register (GPIO208 to 223), 0x1E8
    union GPGMUX1_REG GPGMUX1;   // GPIO G Mux 1 Register (GPIO198 to 207), 0x1EC
    union GPGMUX2_REG GPGMUX2;   // GPIO G Mux 2 Register (GPIO208 to 223), 0x1F0
    union GPGDIR_REG GPGDIR;     // GPIO G Direction Register (GPIO198 to 223), 0x1F4
    union GPGPUD_REG GPGPUD;     // GPIO G Pull Up Disable Register (GPIO198 to 223), 0x1F8
    union GPGINV_REG GPGINV;     // GPIO G Input Polarity Invert Registers (GPIO198 to 223), 0x1FC
    union GPGODR_REG GPGODR;     // GPIO G Open Drain Output Register (GPIO198 to 223), 0x200
    union GPGAMSEL_REG GPGAMSEL; // GPIO G Analog Mode Select register (GPIO198 to 223), 0x204
    union GPGGMUX1_REG GPGGMUX1; // GPIO G Peripheral Group Mux (GPIO198 to 207), 0x208
    union GPGGMUX2_REG GPGGMUX2; // GPIO G Peripheral Group Mux (GPIO208 to 223), 0x20C
    union GPGCSEL1_REG GPGCSEL1; // GPIO G Core Select Register (GPIO198 to 199), 0x210
    union GPGCSEL2_REG GPGCSEL2; // GPIO G Core Select Register (GPIO200 to 207), 0x214
    union GPGCSEL3_REG GPGCSEL3; // GPIO G Core Select Register (GPIO208 to 215), 0x218
    union GPGCSEL4_REG GPGCSEL4; // GPIO G Core Select Register (GPIO216 to 223), 0x21C
    union GPGLOCK_REG GPGLOCK;   // GPIO G Lock Configuration Register (GPIO198 to 223), 0x220
    union GPGCR_REG GPGCR;       // GPIO G Lock Commit Register (GPIO198 to 223), 0x224
    Uint32 rsvd11[2];            // Reserved, 0x228~0x22C
    union GPHCTRL_REG GPHCTRL;   // GPIO H Qualification Sampling Period Control (GPIO224), 0x230
    union GPHQSEL1_REG GPHQSEL1; // GPIO H Qualifier Select 1 Register (GPIO224), 0x234
    union GPHQSEL2_REG GPHQSEL2; // GPIO H Qualifier Select 2 Register Reserved, 0x238
    union GPHMUX1_REG GPHMUX1;   // GPIO H Mux 1 Register (GPIO224), 0x23C
    union GPHMUX2_REG GPHMUX2;   // GPIO H Mux 2 Register (GPIO240), 0x240
    union GPHDIR_REG GPHDIR;     // GPIO H Direction Register (GPIO224), 0x244
    union GPHPUD_REG GPHPUD;     // GPIO H Pull Up Disable Register (GPIO224), 0x248
    union GPHINV_REG GPHINV;     // GPIO H Input Polarity Invert Registers (GPIO224), 0x24C
    union GPHODR_REG GPHODR;     // GPIO H Open Drain Output Register (GPIO224), 0x250
    union GPHAMSEL_REG GPHAMSEL; // GPIO H Analog Mode Select register (GPIO224), 0x254
    union GPHGMUX1_REG GPHGMUX1; // GPIO H Peripheral Group Mux (GPIO224), 0x258
    union GPHGMUX2_REG GPHGMUX2; // GPIO H Peripheral Group Mux Reserved, 0x25C
    union GPHCSEL1_REG GPHCSEL1; // GPIO H Core Select Register (GPIO224), 0x260
    union GPHCSEL2_REG GPHCSEL2; // GPIO H Core Select Register Reserved, 0x264
    union GPHCSEL3_REG GPHCSEL3; // GPIO H Core Select Register Reserved, 0x268
    union GPHCSEL3_REG GPHCSEL4; // GPIO H Core Select Register Reserved, 0x26C
    union GPHLOCK_REG GPHLOCK;   // GPIO H Lock Configuration Register (GPIO224), 0x270
    union GPHCR_REG GPHCR;       // GPIO H Lock Commit Register (GPIO224), 0x274
    /* clang-format on */
};

struct GPADAT_BITS
{                      // bits description
    Uint32 GPIO0  : 1; // 0 Data Register for this pin
    Uint32 GPIO1  : 1; // 1 Data Register for this pin
    Uint32 GPIO2  : 1; // 2 Data Register for this pin
    Uint32 GPIO3  : 1; // 3 Data Register for this pin
    Uint32 GPIO4  : 1; // 4 Data Register for this pin
    Uint32 GPIO5  : 1; // 5 Data Register for this pin
    Uint32 GPIO6  : 1; // 6 Data Register for this pin
    Uint32 GPIO7  : 1; // 7 Data Register for this pin
    Uint32 GPIO8  : 1; // 8 Data Register for this pin
    Uint32 GPIO9  : 1; // 9 Data Register for this pin
    Uint32 GPIO10 : 1; // 10 Data Register for this pin
    Uint32 GPIO11 : 1; // 11 Data Register for this pin
    Uint32 GPIO12 : 1; // 12 Data Register for this pin
    Uint32 GPIO13 : 1; // 13 Data Register for this pin
    Uint32 GPIO14 : 1; // 14 Data Register for this pin
    Uint32 GPIO15 : 1; // 15 Data Register for this pin
    Uint32 GPIO16 : 1; // 16 Data Register for this pin
    Uint32 GPIO17 : 1; // 17 Data Register for this pin
    Uint32 GPIO18 : 1; // 18 Data Register for this pin
    Uint32 GPIO19 : 1; // 19 Data Register for this pin
    Uint32 GPIO20 : 1; // 20 Data Register for this pin
    Uint32 GPIO21 : 1; // 21 Data Register for this pin
    Uint32 GPIO22 : 1; // 22 Data Register for this pin
    Uint32 GPIO23 : 1; // 23 Data Register for this pin
    Uint32 GPIO24 : 1; // 24 Data Register for this pin
    Uint32 GPIO25 : 1; // 25 Data Register for this pin
    Uint32 GPIO26 : 1; // 26 Data Register for this pin
    Uint32 GPIO27 : 1; // 27 Data Register for this pin
    Uint32 GPIO28 : 1; // 28 Data Register for this pin
    Uint32 GPIO29 : 1; // 29 Data Register for this pin
    Uint32 GPIO30 : 1; // 30 Data Register for this pin
    Uint32 GPIO31 : 1; // 31 Data Register for this pin
};

union GPADAT_REG
{
    Uint32 all;
    struct GPADAT_BITS bit;
};

struct GPASET_BITS
{                      // bits description
    Uint32 GPIO0  : 1; // 0 Output Set bit for this pin
    Uint32 GPIO1  : 1; // 1 Output Set bit for this pin
    Uint32 GPIO2  : 1; // 2 Output Set bit for this pin
    Uint32 GPIO3  : 1; // 3 Output Set bit for this pin
    Uint32 GPIO4  : 1; // 4 Output Set bit for this pin
    Uint32 GPIO5  : 1; // 5 Output Set bit for this pin
    Uint32 GPIO6  : 1; // 6 Output Set bit for this pin
    Uint32 GPIO7  : 1; // 7 Output Set bit for this pin
    Uint32 GPIO8  : 1; // 8 Output Set bit for this pin
    Uint32 GPIO9  : 1; // 9 Output Set bit for this pin
    Uint32 GPIO10 : 1; // 10 Output Set bit for this pin
    Uint32 GPIO11 : 1; // 11 Output Set bit for this pin
    Uint32 GPIO12 : 1; // 12 Output Set bit for this pin
    Uint32 GPIO13 : 1; // 13 Output Set bit for this pin
    Uint32 GPIO14 : 1; // 14 Output Set bit for this pin
    Uint32 GPIO15 : 1; // 15 Output Set bit for this pin
    Uint32 GPIO16 : 1; // 16 Output Set bit for this pin
    Uint32 GPIO17 : 1; // 17 Output Set bit for this pin
    Uint32 GPIO18 : 1; // 18 Output Set bit for this pin
    Uint32 GPIO19 : 1; // 19 Output Set bit for this pin
    Uint32 GPIO20 : 1; // 20 Output Set bit for this pin
    Uint32 GPIO21 : 1; // 21 Output Set bit for this pin
    Uint32 GPIO22 : 1; // 22 Output Set bit for this pin
    Uint32 GPIO23 : 1; // 23 Output Set bit for this pin
    Uint32 GPIO24 : 1; // 24 Output Set bit for this pin
    Uint32 GPIO25 : 1; // 25 Output Set bit for this pin
    Uint32 GPIO26 : 1; // 26 Output Set bit for this pin
    Uint32 GPIO27 : 1; // 27 Output Set bit for this pin
    Uint32 GPIO28 : 1; // 28 Output Set bit for this pin
    Uint32 GPIO29 : 1; // 29 Output Set bit for this pin
    Uint32 GPIO30 : 1; // 30 Output Set bit for this pin
    Uint32 GPIO31 : 1; // 31 Output Set bit for this pin
};

union GPASET_REG
{
    Uint32 all;
    struct GPASET_BITS bit;
};

struct GPACLEAR_BITS
{                      // bits description
    Uint32 GPIO0  : 1; // 0 Output Clear bit for this pin
    Uint32 GPIO1  : 1; // 1 Output Clear bit for this pin
    Uint32 GPIO2  : 1; // 2 Output Clear bit for this pin
    Uint32 GPIO3  : 1; // 3 Output Clear bit for this pin
    Uint32 GPIO4  : 1; // 4 Output Clear bit for this pin
    Uint32 GPIO5  : 1; // 5 Output Clear bit for this pin
    Uint32 GPIO6  : 1; // 6 Output Clear bit for this pin
    Uint32 GPIO7  : 1; // 7 Output Clear bit for this pin
    Uint32 GPIO8  : 1; // 8 Output Clear bit for this pin
    Uint32 GPIO9  : 1; // 9 Output Clear bit for this pin
    Uint32 GPIO10 : 1; // 10 Output Clear bit for this pin
    Uint32 GPIO11 : 1; // 11 Output Clear bit for this pin
    Uint32 GPIO12 : 1; // 12 Output Clear bit for this pin
    Uint32 GPIO13 : 1; // 13 Output Clear bit for this pin
    Uint32 GPIO14 : 1; // 14 Output Clear bit for this pin
    Uint32 GPIO15 : 1; // 15 Output Clear bit for this pin
    Uint32 GPIO16 : 1; // 16 Output Clear bit for this pin
    Uint32 GPIO17 : 1; // 17 Output Clear bit for this pin
    Uint32 GPIO18 : 1; // 18 Output Clear bit for this pin
    Uint32 GPIO19 : 1; // 19 Output Clear bit for this pin
    Uint32 GPIO20 : 1; // 20 Output Clear bit for this pin
    Uint32 GPIO21 : 1; // 21 Output Clear bit for this pin
    Uint32 GPIO22 : 1; // 22 Output Clear bit for this pin
    Uint32 GPIO23 : 1; // 23 Output Clear bit for this pin
    Uint32 GPIO24 : 1; // 24 Output Clear bit for this pin
    Uint32 GPIO25 : 1; // 25 Output Clear bit for this pin
    Uint32 GPIO26 : 1; // 26 Output Clear bit for this pin
    Uint32 GPIO27 : 1; // 27 Output Clear bit for this pin
    Uint32 GPIO28 : 1; // 28 Output Clear bit for this pin
    Uint32 GPIO29 : 1; // 29 Output Clear bit for this pin
    Uint32 GPIO30 : 1; // 30 Output Clear bit for this pin
    Uint32 GPIO31 : 1; // 31 Output Clear bit for this pin
};

union GPACLEAR_REG
{
    Uint32 all;
    struct GPACLEAR_BITS bit;
};

struct GPATOGGLE_BITS
{                      // bits description
    Uint32 GPIO0  : 1; // 0 Output Toggle bit for this pin
    Uint32 GPIO1  : 1; // 1 Output Toggle bit for this pin
    Uint32 GPIO2  : 1; // 2 Output Toggle bit for this pin
    Uint32 GPIO3  : 1; // 3 Output Toggle bit for this pin
    Uint32 GPIO4  : 1; // 4 Output Toggle bit for this pin
    Uint32 GPIO5  : 1; // 5 Output Toggle bit for this pin
    Uint32 GPIO6  : 1; // 6 Output Toggle bit for this pin
    Uint32 GPIO7  : 1; // 7 Output Toggle bit for this pin
    Uint32 GPIO8  : 1; // 8 Output Toggle bit for this pin
    Uint32 GPIO9  : 1; // 9 Output Toggle bit for this pin
    Uint32 GPIO10 : 1; // 10 Output Toggle bit for this pin
    Uint32 GPIO11 : 1; // 11 Output Toggle bit for this pin
    Uint32 GPIO12 : 1; // 12 Output Toggle bit for this pin
    Uint32 GPIO13 : 1; // 13 Output Toggle bit for this pin
    Uint32 GPIO14 : 1; // 14 Output Toggle bit for this pin
    Uint32 GPIO15 : 1; // 15 Output Toggle bit for this pin
    Uint32 GPIO16 : 1; // 16 Output Toggle bit for this pin
    Uint32 GPIO17 : 1; // 17 Output Toggle bit for this pin
    Uint32 GPIO18 : 1; // 18 Output Toggle bit for this pin
    Uint32 GPIO19 : 1; // 19 Output Toggle bit for this pin
    Uint32 GPIO20 : 1; // 20 Output Toggle bit for this pin
    Uint32 GPIO21 : 1; // 21 Output Toggle bit for this pin
    Uint32 GPIO22 : 1; // 22 Output Toggle bit for this pin
    Uint32 GPIO23 : 1; // 23 Output Toggle bit for this pin
    Uint32 GPIO24 : 1; // 24 Output Toggle bit for this pin
    Uint32 GPIO25 : 1; // 25 Output Toggle bit for this pin
    Uint32 GPIO26 : 1; // 26 Output Toggle bit for this pin
    Uint32 GPIO27 : 1; // 27 Output Toggle bit for this pin
    Uint32 GPIO28 : 1; // 28 Output Toggle bit for this pin
    Uint32 GPIO29 : 1; // 29 Output Toggle bit for this pin
    Uint32 GPIO30 : 1; // 30 Output Toggle bit for this pin
    Uint32 GPIO31 : 1; // 31 Output Toggle bit for this pin
};

union GPATOGGLE_REG
{
    Uint32 all;
    struct GPATOGGLE_BITS bit;
};

struct GPBDAT_BITS
{                      // bits description
    Uint32 GPIO32 : 1; // 0 Data Register for this pin
    Uint32 GPIO33 : 1; // 1 Data Register for this pin
    Uint32 GPIO34 : 1; // 2 Data Register for this pin
    Uint32 GPIO35 : 1; // 3 Data Register for this pin
    Uint32 GPIO36 : 1; // 4 Data Register for this pin
    Uint32 GPIO37 : 1; // 5 Data Register for this pin
    Uint32 GPIO38 : 1; // 6 Data Register for this pin
    Uint32 GPIO39 : 1; // 7 Data Register for this pin
    Uint32 GPIO40 : 1; // 8 Data Register for this pin
    Uint32 GPIO41 : 1; // 9 Data Register for this pin
    Uint32 GPIO42 : 1; // 10 Data Register for this pin
    Uint32 GPIO43 : 1; // 11 Data Register for this pin
    Uint32 GPIO44 : 1; // 12 Data Register for this pin
    Uint32 GPIO45 : 1; // 13 Data Register for this pin
    Uint32 GPIO46 : 1; // 14 Data Register for this pin
    Uint32 GPIO47 : 1; // 15 Data Register for this pin
    Uint32 GPIO48 : 1; // 16 Data Register for this pin
    Uint32 GPIO49 : 1; // 17 Data Register for this pin
    Uint32 GPIO50 : 1; // 18 Data Register for this pin
    Uint32 GPIO51 : 1; // 19 Data Register for this pin
    Uint32 GPIO52 : 1; // 20 Data Register for this pin
    Uint32 GPIO53 : 1; // 21 Data Register for this pin
    Uint32 GPIO54 : 1; // 22 Data Register for this pin
    Uint32 GPIO55 : 1; // 23 Data Register for this pin
    Uint32 GPIO56 : 1; // 24 Data Register for this pin
    Uint32 GPIO57 : 1; // 25 Data Register for this pin
    Uint32 GPIO58 : 1; // 26 Data Register for this pin
    Uint32 GPIO59 : 1; // 27 Data Register for this pin
    Uint32 GPIO60 : 1; // 28 Data Register for this pin
    Uint32 GPIO61 : 1; // 29 Data Register for this pin
    Uint32 GPIO62 : 1; // 30 Data Register for this pin
    Uint32 GPIO63 : 1; // 31 Data Register for this pin
};

union GPBDAT_REG
{
    Uint32 all;
    struct GPBDAT_BITS bit;
};

struct GPBSET_BITS
{                      // bits description
    Uint32 GPIO32 : 1; // 0 Output Set bit for this pin
    Uint32 GPIO33 : 1; // 1 Output Set bit for this pin
    Uint32 GPIO34 : 1; // 2 Output Set bit for this pin
    Uint32 GPIO35 : 1; // 3 Output Set bit for this pin
    Uint32 GPIO36 : 1; // 4 Output Set bit for this pin
    Uint32 GPIO37 : 1; // 5 Output Set bit for this pin
    Uint32 GPIO38 : 1; // 6 Output Set bit for this pin
    Uint32 GPIO39 : 1; // 7 Output Set bit for this pin
    Uint32 GPIO40 : 1; // 8 Output Set bit for this pin
    Uint32 GPIO41 : 1; // 9 Output Set bit for this pin
    Uint32 GPIO42 : 1; // 10 Output Set bit for this pin
    Uint32 GPIO43 : 1; // 11 Output Set bit for this pin
    Uint32 GPIO44 : 1; // 12 Output Set bit for this pin
    Uint32 GPIO45 : 1; // 13 Output Set bit for this pin
    Uint32 GPIO46 : 1; // 14 Output Set bit for this pin
    Uint32 GPIO47 : 1; // 15 Output Set bit for this pin
    Uint32 GPIO48 : 1; // 16 Output Set bit for this pin
    Uint32 GPIO49 : 1; // 17 Output Set bit for this pin
    Uint32 GPIO50 : 1; // 18 Output Set bit for this pin
    Uint32 GPIO51 : 1; // 19 Output Set bit for this pin
    Uint32 GPIO52 : 1; // 20 Output Set bit for this pin
    Uint32 GPIO53 : 1; // 21 Output Set bit for this pin
    Uint32 GPIO54 : 1; // 22 Output Set bit for this pin
    Uint32 GPIO55 : 1; // 23 Output Set bit for this pin
    Uint32 GPIO56 : 1; // 24 Output Set bit for this pin
    Uint32 GPIO57 : 1; // 25 Output Set bit for this pin
    Uint32 GPIO58 : 1; // 26 Output Set bit for this pin
    Uint32 GPIO59 : 1; // 27 Output Set bit for this pin
    Uint32 GPIO60 : 1; // 28 Output Set bit for this pin
    Uint32 GPIO61 : 1; // 29 Output Set bit for this pin
    Uint32 GPIO62 : 1; // 30 Output Set bit for this pin
    Uint32 GPIO63 : 1; // 31 Output Set bit for this pin
};

union GPBSET_REG
{
    Uint32 all;
    struct GPBSET_BITS bit;
};

struct GPBCLEAR_BITS
{                      // bits description
    Uint32 GPIO32 : 1; // 0 Output Clear bit for this pin
    Uint32 GPIO33 : 1; // 1 Output Clear bit for this pin
    Uint32 GPIO34 : 1; // 2 Output Clear bit for this pin
    Uint32 GPIO35 : 1; // 3 Output Clear bit for this pin
    Uint32 GPIO36 : 1; // 4 Output Clear bit for this pin
    Uint32 GPIO37 : 1; // 5 Output Clear bit for this pin
    Uint32 GPIO38 : 1; // 6 Output Clear bit for this pin
    Uint32 GPIO39 : 1; // 7 Output Clear bit for this pin
    Uint32 GPIO40 : 1; // 8 Output Clear bit for this pin
    Uint32 GPIO41 : 1; // 9 Output Clear bit for this pin
    Uint32 GPIO42 : 1; // 10 Output Clear bit for this pin
    Uint32 GPIO43 : 1; // 11 Output Clear bit for this pin
    Uint32 GPIO44 : 1; // 12 Output Clear bit for this pin
    Uint32 GPIO45 : 1; // 13 Output Clear bit for this pin
    Uint32 GPIO46 : 1; // 14 Output Clear bit for this pin
    Uint32 GPIO47 : 1; // 15 Output Clear bit for this pin
    Uint32 GPIO48 : 1; // 16 Output Clear bit for this pin
    Uint32 GPIO49 : 1; // 17 Output Clear bit for this pin
    Uint32 GPIO50 : 1; // 18 Output Clear bit for this pin
    Uint32 GPIO51 : 1; // 19 Output Clear bit for this pin
    Uint32 GPIO52 : 1; // 20 Output Clear bit for this pin
    Uint32 GPIO53 : 1; // 21 Output Clear bit for this pin
    Uint32 GPIO54 : 1; // 22 Output Clear bit for this pin
    Uint32 GPIO55 : 1; // 23 Output Clear bit for this pin
    Uint32 GPIO56 : 1; // 24 Output Clear bit for this pin
    Uint32 GPIO57 : 1; // 25 Output Clear bit for this pin
    Uint32 GPIO58 : 1; // 26 Output Clear bit for this pin
    Uint32 GPIO59 : 1; // 27 Output Clear bit for this pin
    Uint32 GPIO60 : 1; // 28 Output Clear bit for this pin
    Uint32 GPIO61 : 1; // 29 Output Clear bit for this pin
    Uint32 GPIO62 : 1; // 30 Output Clear bit for this pin
    Uint32 GPIO63 : 1; // 31 Output Clear bit for this pin
};

union GPBCLEAR_REG
{
    Uint32 all;
    struct GPBCLEAR_BITS bit;
};

struct GPBTOGGLE_BITS
{                      // bits description
    Uint32 GPIO32 : 1; // 0 Output Toggle bit for this pin
    Uint32 GPIO33 : 1; // 1 Output Toggle bit for this pin
    Uint32 GPIO34 : 1; // 2 Output Toggle bit for this pin
    Uint32 GPIO35 : 1; // 3 Output Toggle bit for this pin
    Uint32 GPIO36 : 1; // 4 Output Toggle bit for this pin
    Uint32 GPIO37 : 1; // 5 Output Toggle bit for this pin
    Uint32 GPIO38 : 1; // 6 Output Toggle bit for this pin
    Uint32 GPIO39 : 1; // 7 Output Toggle bit for this pin
    Uint32 GPIO40 : 1; // 8 Output Toggle bit for this pin
    Uint32 GPIO41 : 1; // 9 Output Toggle bit for this pin
    Uint32 GPIO42 : 1; // 10 Output Toggle bit for this pin
    Uint32 GPIO43 : 1; // 11 Output Toggle bit for this pin
    Uint32 GPIO44 : 1; // 12 Output Toggle bit for this pin
    Uint32 GPIO45 : 1; // 13 Output Toggle bit for this pin
    Uint32 GPIO46 : 1; // 14 Output Toggle bit for this pin
    Uint32 GPIO47 : 1; // 15 Output Toggle bit for this pin
    Uint32 GPIO48 : 1; // 16 Output Toggle bit for this pin
    Uint32 GPIO49 : 1; // 17 Output Toggle bit for this pin
    Uint32 GPIO50 : 1; // 18 Output Toggle bit for this pin
    Uint32 GPIO51 : 1; // 19 Output Toggle bit for this pin
    Uint32 GPIO52 : 1; // 20 Output Toggle bit for this pin
    Uint32 GPIO53 : 1; // 21 Output Toggle bit for this pin
    Uint32 GPIO54 : 1; // 22 Output Toggle bit for this pin
    Uint32 GPIO55 : 1; // 23 Output Toggle bit for this pin
    Uint32 GPIO56 : 1; // 24 Output Toggle bit for this pin
    Uint32 GPIO57 : 1; // 25 Output Toggle bit for this pin
    Uint32 GPIO58 : 1; // 26 Output Toggle bit for this pin
    Uint32 GPIO59 : 1; // 27 Output Toggle bit for this pin
    Uint32 GPIO60 : 1; // 28 Output Toggle bit for this pin
    Uint32 GPIO61 : 1; // 29 Output Toggle bit for this pin
    Uint32 GPIO62 : 1; // 30 Output Toggle bit for this pin
    Uint32 GPIO63 : 1; // 31 Output Toggle bit for this pin
};

union GPBTOGGLE_REG
{
    Uint32 all;
    struct GPBTOGGLE_BITS bit;
};

struct GPCDAT_BITS
{                      // bits description
    Uint32 GPIO64 : 1; // 0 Data Register for this pin
    Uint32 GPIO65 : 1; // 1 Data Register for this pin
    Uint32 GPIO66 : 1; // 2 Data Register for this pin
    Uint32 GPIO67 : 1; // 3 Data Register for this pin
    Uint32 GPIO68 : 1; // 4 Data Register for this pin
    Uint32 GPIO69 : 1; // 5 Data Register for this pin
    Uint32 GPIO70 : 1; // 6 Data Register for this pin
    Uint32 GPIO71 : 1; // 7 Data Register for this pin
    Uint32 GPIO72 : 1; // 8 Data Register for this pin
    Uint32 GPIO73 : 1; // 9 Data Register for this pin
    Uint32 GPIO74 : 1; // 10 Data Register for this pin
    Uint32 GPIO75 : 1; // 11 Data Register for this pin
    Uint32 GPIO76 : 1; // 12 Data Register for this pin
    Uint32 GPIO77 : 1; // 13 Data Register for this pin
    Uint32 GPIO78 : 1; // 14 Data Register for this pin
    Uint32 GPIO79 : 1; // 15 Data Register for this pin
    Uint32 GPIO80 : 1; // 16 Data Register for this pin
    Uint32 GPIO81 : 1; // 17 Data Register for this pin
    Uint32 GPIO82 : 1; // 18 Data Register for this pin
    Uint32 GPIO83 : 1; // 19 Data Register for this pin
    Uint32 GPIO84 : 1; // 20 Data Register for this pin
    Uint32 GPIO85 : 1; // 21 Data Register for this pin
    Uint32 GPIO86 : 1; // 22 Data Register for this pin
    Uint32 GPIO87 : 1; // 23 Data Register for this pin
    Uint32 GPIO88 : 1; // 24 Data Register for this pin
    Uint32 GPIO89 : 1; // 25 Data Register for this pin
    Uint32 GPIO90 : 1; // 26 Data Register for this pin
    Uint32 GPIO91 : 1; // 27 Data Register for this pin
    Uint32 GPIO92 : 1; // 28 Data Register for this pin
    Uint32 GPIO93 : 1; // 29 Data Register for this pin
    Uint32 GPIO94 : 1; // 30 Data Register for this pin
    Uint32 rsvd   : 1;
};

union GPCDAT_REG
{
    Uint32 all;
    struct GPCDAT_BITS bit;
};

struct GPCSET_BITS
{                      // bits description
    Uint32 GPIO64 : 1; // 0 Output Set bit for this pin
    Uint32 GPIO65 : 1; // 1 Output Set bit for this pin
    Uint32 GPIO66 : 1; // 2 Output Set bit for this pin
    Uint32 GPIO67 : 1; // 3 Output Set bit for this pin
    Uint32 GPIO68 : 1; // 4 Output Set bit for this pin
    Uint32 GPIO69 : 1; // 5 Output Set bit for this pin
    Uint32 GPIO70 : 1; // 6 Output Set bit for this pin
    Uint32 GPIO71 : 1; // 7 Output Set bit for this pin
    Uint32 GPIO72 : 1; // 8 Output Set bit for this pin
    Uint32 GPIO73 : 1; // 9 Output Set bit for this pin
    Uint32 GPIO74 : 1; // 10 Output Set bit for this pin
    Uint32 GPIO75 : 1; // 11 Output Set bit for this pin
    Uint32 GPIO76 : 1; // 12 Output Set bit for this pin
    Uint32 GPIO77 : 1; // 13 Output Set bit for this pin
    Uint32 GPIO78 : 1; // 14 Output Set bit for this pin
    Uint32 GPIO79 : 1; // 15 Output Set bit for this pin
    Uint32 GPIO80 : 1; // 16 Output Set bit for this pin
    Uint32 GPIO81 : 1; // 17 Output Set bit for this pin
    Uint32 GPIO82 : 1; // 18 Output Set bit for this pin
    Uint32 GPIO83 : 1; // 19 Output Set bit for this pin
    Uint32 GPIO84 : 1; // 20 Output Set bit for this pin
    Uint32 GPIO85 : 1; // 21 Output Set bit for this pin
    Uint32 GPIO86 : 1; // 22 Output Set bit for this pin
    Uint32 GPIO87 : 1; // 23 Output Set bit for this pin
    Uint32 GPIO88 : 1; // 24 Output Set bit for this pin
    Uint32 GPIO89 : 1; // 25 Output Set bit for this pin
    Uint32 GPIO90 : 1; // 26 Output Set bit for this pin
    Uint32 GPIO91 : 1; // 27 Output Set bit for this pin
    Uint32 GPIO92 : 1; // 28 Output Set bit for this pin
    Uint32 GPIO93 : 1; // 29 Output Set bit for this pin
    Uint32 GPIO94 : 1; // 30 Output Set bit for this pin
    Uint32 rsvd   : 1;
};

union GPCSET_REG
{
    Uint32 all;
    struct GPCSET_BITS bit;
};

struct GPCCLEAR_BITS
{                      // bits description
    Uint32 GPIO64 : 1; // 0 Output Clear bit for this pin
    Uint32 GPIO65 : 1; // 1 Output Clear bit for this pin
    Uint32 GPIO66 : 1; // 2 Output Clear bit for this pin
    Uint32 GPIO67 : 1; // 3 Output Clear bit for this pin
    Uint32 GPIO68 : 1; // 4 Output Clear bit for this pin
    Uint32 GPIO69 : 1; // 5 Output Clear bit for this pin
    Uint32 GPIO70 : 1; // 6 Output Clear bit for this pin
    Uint32 GPIO71 : 1; // 7 Output Clear bit for this pin
    Uint32 GPIO72 : 1; // 8 Output Clear bit for this pin
    Uint32 GPIO73 : 1; // 9 Output Clear bit for this pin
    Uint32 GPIO74 : 1; // 10 Output Clear bit for this pin
    Uint32 GPIO75 : 1; // 11 Output Clear bit for this pin
    Uint32 GPIO76 : 1; // 12 Output Clear bit for this pin
    Uint32 GPIO77 : 1; // 13 Output Clear bit for this pin
    Uint32 GPIO78 : 1; // 14 Output Clear bit for this pin
    Uint32 GPIO79 : 1; // 15 Output Clear bit for this pin
    Uint32 GPIO80 : 1; // 16 Output Clear bit for this pin
    Uint32 GPIO81 : 1; // 17 Output Clear bit for this pin
    Uint32 GPIO82 : 1; // 18 Output Clear bit for this pin
    Uint32 GPIO83 : 1; // 19 Output Clear bit for this pin
    Uint32 GPIO84 : 1; // 20 Output Clear bit for this pin
    Uint32 GPIO85 : 1; // 21 Output Clear bit for this pin
    Uint32 GPIO86 : 1; // 22 Output Clear bit for this pin
    Uint32 GPIO87 : 1; // 23 Output Clear bit for this pin
    Uint32 GPIO88 : 1; // 24 Output Clear bit for this pin
    Uint32 GPIO89 : 1; // 25 Output Clear bit for this pin
    Uint32 GPIO90 : 1; // 26 Output Clear bit for this pin
    Uint32 GPIO91 : 1; // 27 Output Clear bit for this pin
    Uint32 GPIO92 : 1; // 28 Output Clear bit for this pin
    Uint32 GPIO93 : 1; // 29 Output Clear bit for this pin
    Uint32 GPIO94 : 1; // 30 Output Clear bit for this pin
    Uint32 rsvd   : 1;
};

union GPCCLEAR_REG
{
    Uint32 all;
    struct GPCCLEAR_BITS bit;
};

struct GPCTOGGLE_BITS
{                      // bits description
    Uint32 GPIO64 : 1; // 0 Output Toggle bit for this pin
    Uint32 GPIO65 : 1; // 1 Output Toggle bit for this pin
    Uint32 GPIO66 : 1; // 2 Output Toggle bit for this pin
    Uint32 GPIO67 : 1; // 3 Output Toggle bit for this pin
    Uint32 GPIO68 : 1; // 4 Output Toggle bit for this pin
    Uint32 GPIO69 : 1; // 5 Output Toggle bit for this pin
    Uint32 GPIO70 : 1; // 6 Output Toggle bit for this pin
    Uint32 GPIO71 : 1; // 7 Output Toggle bit for this pin
    Uint32 GPIO72 : 1; // 8 Output Toggle bit for this pin
    Uint32 GPIO73 : 1; // 9 Output Toggle bit for this pin
    Uint32 GPIO74 : 1; // 10 Output Toggle bit for this pin
    Uint32 GPIO75 : 1; // 11 Output Toggle bit for this pin
    Uint32 GPIO76 : 1; // 12 Output Toggle bit for this pin
    Uint32 GPIO77 : 1; // 13 Output Toggle bit for this pin
    Uint32 GPIO78 : 1; // 14 Output Toggle bit for this pin
    Uint32 GPIO79 : 1; // 15 Output Toggle bit for this pin
    Uint32 GPIO80 : 1; // 16 Output Toggle bit for this pin
    Uint32 GPIO81 : 1; // 17 Output Toggle bit for this pin
    Uint32 GPIO82 : 1; // 18 Output Toggle bit for this pin
    Uint32 GPIO83 : 1; // 19 Output Toggle bit for this pin
    Uint32 GPIO84 : 1; // 20 Output Toggle bit for this pin
    Uint32 GPIO85 : 1; // 21 Output Toggle bit for this pin
    Uint32 GPIO86 : 1; // 22 Output Toggle bit for this pin
    Uint32 GPIO87 : 1; // 23 Output Toggle bit for this pin
    Uint32 GPIO88 : 1; // 24 Output Toggle bit for this pin
    Uint32 GPIO89 : 1; // 25 Output Toggle bit for this pin
    Uint32 GPIO90 : 1; // 26 Output Toggle bit for this pin
    Uint32 GPIO91 : 1; // 27 Output Toggle bit for this pin
    Uint32 GPIO92 : 1; // 28 Output Toggle bit for this pin
    Uint32 GPIO93 : 1; // 29 Output Toggle bit for this pin
    Uint32 GPIO94 : 1; // 30 Output Toggle bit for this pin
    Uint32 rsvd   : 1;
};

union GPCTOGGLE_REG
{
    Uint32 all;
    struct GPCTOGGLE_BITS bit;
};

struct GPDDAT_BITS
{ // bits description
    Uint32 rsvd0   : 3;
    Uint32 GPIO99  : 1; // 3 Data Register for this pin
    Uint32 GPIO100 : 1; // 4 Data Register for this pin
    Uint32 rsvd1   : 2;
    Uint32 GPIO103 : 1; // 7 Data Register for this pin
    Uint32 GPIO104 : 1; // 8 Data Register for this pin
    Uint32 GPIO105 : 1; // 9 Data Register for this pin
    Uint32 GPIO106 : 1; // 10 Data Register for this pin
};

union GPDDAT_REG
{
    Uint32 all;
    struct GPDDAT_BITS bit;
};

struct GPDSET_BITS
{ // bits description
    Uint32 rsvd0   : 3;
    Uint32 GPIO99  : 1; // 3 Output Set bit for this pin
    Uint32 GPIO100 : 1; // 4 Output Set bit for this pin
    Uint32 rsvd1   : 2;
    Uint32 GPIO103 : 1; // 7 Output Set bit for this pin
    Uint32 GPIO104 : 1; // 8 Output Set bit for this pin
    Uint32 GPIO105 : 1; // 9 Output Set bit for this pin
    Uint32 GPIO106 : 1; // 10 Output Set bit for this pin
};

union GPDSET_REG
{
    Uint32 all;
    struct GPDSET_BITS bit;
};

struct GPDCLEAR_BITS
{                       // bits description
    Uint32 rsvd0   : 3; // 0 Output Clear bit for this pin
    Uint32 GPIO99  : 1; // 3 Output Clear bit for this pin
    Uint32 GPIO100 : 1; // 4 Output Clear bit for this pin
    Uint32 rsvd1   : 2;
    Uint32 GPIO103 : 1; // 7 Output Clear bit for this pin
    Uint32 GPIO104 : 1; // 8 Output Clear bit for this pin
    Uint32 GPIO105 : 1; // 9 Output Clear bit for this pin
    Uint32 GPIO106 : 1; // 10 Output Clear bit for this pin
};

union GPDCLEAR_REG
{
    Uint32 all;
    struct GPDCLEAR_BITS bit;
};

struct GPDTOGGLE_BITS
{ // bits description
    Uint32 rsvd0   : 3;
    Uint32 GPIO99  : 1; // 3 Output Toggle bit for this pin
    Uint32 GPIO100 : 1; // 4 Output Toggle bit for this pin
    Uint32 rsvd1   : 2;
    Uint32 GPIO103 : 1; // 7 Output Toggle bit for this pin
    Uint32 GPIO104 : 1; // 8 Output Toggle bit for this pin
    Uint32 GPIO105 : 1; // 9 Output Toggle bit for this pin
    Uint32 GPIO106 : 1; // 10 Output Toggle bit for this pin
};

union GPDTOGGLE_REG
{
    Uint32 all;
    struct GPDTOGGLE_BITS bit;
};

struct GPEDAT_BITS
{ // bits description
    Uint32 rsvd0   : 5;
    Uint32 GPIO133 : 1; // 5 Data Register for this pin
};

union GPEDAT_REG
{
    Uint32 all;
    struct GPEDAT_BITS bit;
};

struct GPESET_BITS
{ // bits description
    Uint32 rsvd0   : 5;
    Uint32 GPIO133 : 1; // 5 Output Set bit for this pin
};

union GPESET_REG
{
    Uint32 all;
    struct GPESET_BITS bit;
};

struct GPECLEAR_BITS
{ // bits description
    Uint32 rsvd0   : 5;
    Uint32 GPIO133 : 1; // 5 Output Clear bit for this pin
};

union GPECLEAR_REG
{
    Uint32 all;
    struct GPECLEAR_BITS bit;
};

struct GPETOGGLE_BITS
{ // bits description
    Uint32 rsvd0   : 5;
    Uint32 GPIO133 : 1; // 5 Output Toggle bit for this pin
};

union GPETOGGLE_REG
{
    Uint32 all;
    struct GPETOGGLE_BITS bit;
};

struct GPGDAT_BITS
{                       // bits description
    Uint32 rsvd1   : 1; // 0 Reserved
    Uint32 rsvd2   : 1; // 1 Reserved
    Uint32 rsvd3   : 1; // 2 Reserved
    Uint32 rsvd4   : 1; // 3 Reserved
    Uint32 rsvd5   : 1; // 4 Reserved
    Uint32 rsvd6   : 1; // 5 Reserved
    Uint32 GPIO198 : 1; // 6 Data Register for this pin
    Uint32 GPIO199 : 1; // 7 Data Register for this pin
    Uint32 GPIO200 : 1; // 8 Data Register for this pin
    Uint32 GPIO201 : 1; // 9 Data Register for this pin
    Uint32 GPIO202 : 1; // 10 Data Register for this pin
    Uint32 GPIO203 : 1; // 11 Data Register for this pin
    Uint32 GPIO204 : 1; // 12 Data Register for this pin
    Uint32 GPIO205 : 1; // 13 Data Register for this pin
    Uint32 GPIO206 : 1; // 14 Data Register for this pin
    Uint32 GPIO207 : 1; // 15 Data Register for this pin
    Uint32 GPIO208 : 1; // 16 Data Register for this pin
    Uint32 GPIO209 : 1; // 17 Data Register for this pin
    Uint32 GPIO210 : 1; // 18 Data Register for this pin
    Uint32 GPIO211 : 1; // 19 Data Register for this pin
    Uint32 GPIO212 : 1; // 20 Data Register for this pin
    Uint32 GPIO213 : 1; // 21 Data Register for this pin
    Uint32 GPIO214 : 1; // 22 Data Register for this pin
    Uint32 GPIO215 : 1; // 23 Data Register for this pin
    Uint32 GPIO216 : 1; // 24 Data Register for this pin
    Uint32 GPIO217 : 1; // 25 Data Register for this pin
    Uint32 GPIO218 : 1; // 26 Data Register for this pin
    Uint32 GPIO219 : 1; // 27 Data Register for this pin
    Uint32 GPIO220 : 1; // 28 Data Register for this pin
    Uint32 GPIO221 : 1; // 29 Data Register for this pin
    Uint32 GPIO222 : 1; // 30 Data Register for this pin
    Uint32 GPIO223 : 1; // 31 Data Register for this pin
};

union GPGDAT_REG
{
    Uint32 all;
    struct GPGDAT_BITS bit;
};

struct GPGSET_BITS
{                       // bits description
    Uint32 rsvd1   : 1; // 0 Reserved
    Uint32 rsvd2   : 1; // 1 Reserved
    Uint32 rsvd3   : 1; // 2 Reserved
    Uint32 rsvd4   : 1; // 3 Reserved
    Uint32 rsvd5   : 1; // 4 Reserved
    Uint32 rsvd6   : 1; // 5 Reserved
    Uint32 GPIO198 : 1; // 6 Output Set bit for this pin
    Uint32 GPIO199 : 1; // 7 Output Set bit for this pin
    Uint32 GPIO200 : 1; // 8 Output Set bit for this pin
    Uint32 GPIO201 : 1; // 9 Output Set bit for this pin
    Uint32 GPIO202 : 1; // 10 Output Set bit for this pin
    Uint32 GPIO203 : 1; // 11 Output Set bit for this pin
    Uint32 GPIO204 : 1; // 12 Output Set bit for this pin
    Uint32 GPIO205 : 1; // 13 Output Set bit for this pin
    Uint32 GPIO206 : 1; // 14 Output Set bit for this pin
    Uint32 GPIO207 : 1; // 15 Output Set bit for this pin
    Uint32 GPIO208 : 1; // 16 Output Set bit for this pin
    Uint32 GPIO209 : 1; // 17 Output Set bit for this pin
    Uint32 GPIO210 : 1; // 18 Output Set bit for this pin
    Uint32 GPIO211 : 1; // 19 Output Set bit for this pin
    Uint32 GPIO212 : 1; // 20 Output Set bit for this pin
    Uint32 GPIO213 : 1; // 21 Output Set bit for this pin
    Uint32 GPIO214 : 1; // 22 Output Set bit for this pin
    Uint32 GPIO215 : 1; // 23 Output Set bit for this pin
    Uint32 GPIO216 : 1; // 24 Output Set bit for this pin
    Uint32 GPIO217 : 1; // 25 Output Set bit for this pin
    Uint32 GPIO218 : 1; // 26 Output Set bit for this pin
    Uint32 GPIO219 : 1; // 27 Output Set bit for this pin
    Uint32 GPIO220 : 1; // 28 Output Set bit for this pin
    Uint32 GPIO221 : 1; // 29 Output Set bit for this pin
    Uint32 GPIO222 : 1; // 30 Output Set bit for this pin
    Uint32 GPIO223 : 1; // 31 Output Set bit for this pin
};

union GPGSET_REG
{
    Uint32 all;
    struct GPGSET_BITS bit;
};

struct GPGCLEAR_BITS
{                       // bits description
    Uint32 rsvd1   : 1; // 0 Reserved
    Uint32 rsvd2   : 1; // 1 Reserved
    Uint32 rsvd3   : 1; // 2 Reserved
    Uint32 rsvd4   : 1; // 3 Reserved
    Uint32 rsvd5   : 1; // 4 Reserved
    Uint32 rsvd6   : 1; // 5 Reserved
    Uint32 GPIO198 : 1; // 6 Output Clear bit for this pin
    Uint32 GPIO199 : 1; // 7 Output Clear bit for this pin
    Uint32 GPIO200 : 1; // 8 Output Clear bit for this pin
    Uint32 GPIO201 : 1; // 9 Output Clear bit for this pin
    Uint32 GPIO202 : 1; // 10 Output Clear bit for this pin
    Uint32 GPIO203 : 1; // 11 Output Clear bit for this pin
    Uint32 GPIO204 : 1; // 12 Output Clear bit for this pin
    Uint32 GPIO205 : 1; // 13 Output Clear bit for this pin
    Uint32 GPIO206 : 1; // 14 Output Clear bit for this pin
    Uint32 GPIO207 : 1; // 15 Output Clear bit for this pin
    Uint32 GPIO208 : 1; // 16 Output Clear bit for this pin
    Uint32 GPIO209 : 1; // 17 Output Clear bit for this pin
    Uint32 GPIO210 : 1; // 18 Output Clear bit for this pin
    Uint32 GPIO211 : 1; // 19 Output Clear bit for this pin
    Uint32 GPIO212 : 1; // 20 Output Clear bit for this pin
    Uint32 GPIO213 : 1; // 21 Output Clear bit for this pin
    Uint32 GPIO214 : 1; // 22 Output Clear bit for this pin
    Uint32 GPIO215 : 1; // 23 Output Clear bit for this pin
    Uint32 GPIO216 : 1; // 24 Output Clear bit for this pin
    Uint32 GPIO217 : 1; // 25 Output Clear bit for this pin
    Uint32 GPIO218 : 1; // 26 Output Clear bit for this pin
    Uint32 GPIO219 : 1; // 27 Output Clear bit for this pin
    Uint32 GPIO220 : 1; // 28 Output Clear bit for this pin
    Uint32 GPIO221 : 1; // 29 Output Clear bit for this pin
    Uint32 GPIO222 : 1; // 30 Output Clear bit for this pin
    Uint32 GPIO223 : 1; // 31 Output Clear bit for this pin
};

union GPGCLEAR_REG
{
    Uint32 all;
    struct GPGCLEAR_BITS bit;
};

struct GPGTOGGLE_BITS
{                       // bits description
    Uint32 rsvd1   : 1; // 0 Reserved
    Uint32 rsvd2   : 1; // 1 Reserved
    Uint32 rsvd3   : 1; // 2 Reserved
    Uint32 rsvd4   : 1; // 3 Reserved
    Uint32 rsvd5   : 1; // 4 Reserved
    Uint32 rsvd6   : 1; // 5 Reserved
    Uint32 GPIO198 : 1; // 6 Output Toggle bit for this pin
    Uint32 GPIO199 : 1; // 7 Output Toggle bit for this pin
    Uint32 GPIO200 : 1; // 8 Output Toggle bit for this pin
    Uint32 GPIO201 : 1; // 9 Output Toggle bit for this pin
    Uint32 GPIO202 : 1; // 10 Output Toggle bit for this pin
    Uint32 GPIO203 : 1; // 11 Output Toggle bit for this pin
    Uint32 GPIO204 : 1; // 12 Output Toggle bit for this pin
    Uint32 GPIO205 : 1; // 13 Output Toggle bit for this pin
    Uint32 GPIO206 : 1; // 14 Output Toggle bit for this pin
    Uint32 GPIO207 : 1; // 15 Output Toggle bit for this pin
    Uint32 GPIO208 : 1; // 16 Output Toggle bit for this pin
    Uint32 GPIO209 : 1; // 17 Output Toggle bit for this pin
    Uint32 GPIO210 : 1; // 18 Output Toggle bit for this pin
    Uint32 GPIO211 : 1; // 19 Output Toggle bit for this pin
    Uint32 GPIO212 : 1; // 20 Output Toggle bit for this pin
    Uint32 GPIO213 : 1; // 21 Output Toggle bit for this pin
    Uint32 GPIO214 : 1; // 22 Output Toggle bit for this pin
    Uint32 GPIO215 : 1; // 23 Output Toggle bit for this pin
    Uint32 GPIO216 : 1; // 24 Output Toggle bit for this pin
    Uint32 GPIO217 : 1; // 25 Output Toggle bit for this pin
    Uint32 GPIO218 : 1; // 26 Output Toggle bit for this pin
    Uint32 GPIO219 : 1; // 27 Output Toggle bit for this pin
    Uint32 GPIO220 : 1; // 28 Output Toggle bit for this pin
    Uint32 GPIO221 : 1; // 29 Output Toggle bit for this pin
    Uint32 GPIO222 : 1; // 30 Output Toggle bit for this pin
    Uint32 GPIO223 : 1; // 31 Output Toggle bit for this pin
};

union GPGTOGGLE_REG
{
    Uint32 all;
    struct GPGTOGGLE_BITS bit;
};

struct GPHDAT_BITS
{                       // bits description
    Uint32 GPIO224 : 1; // 0 Data Register for this pin
};

union GPHDAT_REG
{
    Uint32 all;
    struct GPHDAT_BITS bit;
};

struct GPHSET_BITS
{                       // bits description
    Uint32 GPIO224 : 1; // 0 Output Set bit for this pin
};

union GPHSET_REG
{
    Uint32 all;
    struct GPHSET_BITS bit;
};

struct GPHCLEAR_BITS
{                       // bits description
    Uint32 GPIO224 : 1; // 0 Output Clear bit for this pin
};

union GPHCLEAR_REG
{
    Uint32 all;
    struct GPHCLEAR_BITS bit;
};

struct GPHTOGGLE_BITS
{                       // bits description
    Uint32 GPIO224 : 1; // 0 Output Toggle bit for this pin
};

union GPHTOGGLE_REG
{
    Uint32 all;
    struct GPHTOGGLE_BITS bit;
};

struct GPIO_DATA_REGS
{
    union GPADAT_REG GPADAT;       // GPIO A Data Register (GPIO0 to 31)
    union GPASET_REG GPASET;       // GPIO A Data Set Register (GPIO0 to 31)
    union GPACLEAR_REG GPACLEAR;   // GPIO A Data Clear Register (GPIO0 to 31)
    union GPATOGGLE_REG GPATOGGLE; // GPIO A Data Toggle Register (GPIO0 to 31)
    union GPBDAT_REG GPBDAT;       // GPIO B Data Register (GPIO32 to 63)
    union GPBSET_REG GPBSET;       // GPIO B Data Set Register (GPIO32 to 63)
    union GPBCLEAR_REG GPBCLEAR;   // GPIO B Data Clear Register (GPIO32 to 63)
    union GPBTOGGLE_REG GPBTOGGLE; // GPIO B Data Toggle Register (GPIO32 to 63)
    union GPCDAT_REG GPCDAT;       // GPIO C Data Register (GPIO64 to 94)
    union GPCSET_REG GPCSET;       // GPIO C Data Set Register (GPIO64 to 94)
    union GPCCLEAR_REG GPCCLEAR;   // GPIO C Data Clear Register (GPIO64 to 94)
    union GPCTOGGLE_REG GPCTOGGLE; // GPIO C Data Toggle Register (GPIO64 to 94)
    union GPDDAT_REG GPDDAT;       // GPIO D Data Register (GPIO96 to 127)
    union GPDSET_REG GPDSET;       // GPIO D Data Set Register (GPIO96 to 127)
    union GPDCLEAR_REG GPDCLEAR;   // GPIO D Data Clear Register (GPIO96 to 127)
    union GPDTOGGLE_REG GPDTOGGLE; // GPIO D Data Toggle Register (GPIO96 to 127)
    union GPEDAT_REG GPEDAT;       // GPIO E Data Register (GPIO133)
    union GPESET_REG GPESET;       // GPIO E Data Set Register (GPIO133)
    union GPECLEAR_REG GPECLEAR;   // GPIO E Data Clear Register (GPIO133)
    union GPETOGGLE_REG GPETOGGLE; // GPIO E Data Toggle Register (GPIO133)
    Uint32 rsvd0[4];               // GPIO F all Reserved
    union GPGDAT_REG GPGDAT;       // GPIO G Data Register (GPIO198 to 223)
    union GPGSET_REG GPGSET;       // GPIO G Data Set Register (GPIO198 to 223)
    union GPGCLEAR_REG GPGCLEAR;   // GPIO G Data Clear Register (GPIO198 to 223)
    union GPGTOGGLE_REG GPGTOGGLE; // GPIO G Data Toggle Register (GPIO198 to 223)
    union GPHDAT_REG GPHDAT;       // GPIO H Data Register (GPIO224 to 255)
    union GPHSET_REG GPHSET;       // GPIO H Data Set Register (GPIO224 to 255)
    union GPHCLEAR_REG GPHCLEAR;   // GPIO H Data Clear Register (GPIO224 to 255)
    union GPHTOGGLE_REG GPHTOGGLE; // GPIO H Data Toggle Register (GPIO224 to 255)
};

struct GPIO_DATA_READ_REGS
{
    Uint32 GPADAT_R; // GPIO A Data Read Register
    Uint32 GPBDAT_R; // GPIO B Data Read Register
    Uint32 GPCDAT_R; // GPIO C Data Read Register
    Uint32 GPDDAT_R; // GPIO D Data Read Register
    Uint32 GPEDAT_R; // GPIO E Data Read Register
    Uint32 rsvd;     // GPIO F all Reserved
    Uint32 GPGDAT_R; // GPIO G Data Read Register
    Uint32 GPHDAT_R; // GPIO H Data Read Register
};

//---------------------------------------------------------------------------
// GPIO External References & Function Declarations:
//
#ifdef __CORE0__
extern volatile struct GPIO_CTRL_REGS GpioCtrlRegs;
#endif
extern volatile struct GPIO_DATA_REGS GpioDataRegs;
extern volatile struct GPIO_DATA_READ_REGS GpioDataReadRegs;

extern volatile struct GPIO_DATA_REGS GpioDataClaRegs;
extern volatile struct GPIO_DATA_READ_REGS GpioDataClaReadRegs;
#ifdef __cplusplus
}
#endif /* extern "C" */

#endif

//===========================================================================
// End of file.
//===========================================================================
